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CMOS VLSI Design & Sub Systems of Digital Circuits

Name: CMOS VLSI Design & Sub Systems of Digital Circuits
Rating: 4.7 (158 reviews)

Best VLSI Training Course for starting your career in VLSI Design& Subsystems of MOS circuits (schematic,stick,layouts)

Highest Rated

Created bySkillGems Education

Last updated 10/2023

English

What you'll learn

Basic Plannar Process or Fabrication process of an Integrated Chip
Basic Electrical Properties of MOS and BiCMOS Circuits
MOS & BiCMOS circuit design process (Including Stick and Layouts)
Basic circuits of NMOS, PMOS and CMOS circuits & Scaling of circuits
Subsystem design of digital circuits (includes combinational digital circuits)

Course content

5 sections • 71 lectures • 10h 54m total length

Fabrication of IC using plannar technology4:26
Explore the planar fabrication process for integrated circuits, covering wafer preparation, epitaxial growth, oxidation, photolithography, diffusion, ion implantation, isolation, metallization, assembly, and packaging.
Epitaxial growth1:34
Thermal oxidation1:25
Photolithography1:50
Diffusion1:26
Ion implantation1:05
Metalization1:11
Explore the metallization process for CMOS VLSI interconnections, detailing aluminum thin films deposited by vacuum evaporation and electron-beam heating, their conduction properties, thickness, and subsequent testing and packaging.
Testing bonding packaging1:52

NMOS fabrication20:14
CMOS fabricarion22:42
Introduction8:46
Explore how a p-substrate NMOS forms a gate-controlled channel that allows electrons to flow from source to drain. Analyze transit time, non-saturated and saturated regions, pinch-off, and gate-oxide capacitor behavior.
Ids versus Vds realtion in non saturated condition11:17
Ids versus Vds realtion in saturated condition10:05
Explain Ids–Vds behavior: in the linear region Ids rises with Vds until Vds reaches Vgs−Vt, then pinch-off fixes Ids in saturation; compare enhancement and depletion mode MOSFETs.
vlsi design unit2.1 questions
quiz2
gm and gds14:11
nmos inverter16:54
nmos driven by another nmos11:47
Calculate the pull-up to pull-down ratio for a depletion-mode pull-up NMOS driving an enhancement-mode pull-down NMOS in two cascaded inverters, yielding a 4:1 ratio.
pass transistor2:18
mnos driven by another nmos transistor using pass transistors17:04
alternative forms of pull up12:21
Explore alternative pull-up forms in CMOS VLSI design, including resistor pull-up, depletion-mode and enhancement-mode transistors, and CMOS inverter configurations. Assess output behavior and trade-offs in power, space, and fabrication.
alternative forms of pull up contd.,12:05
explore alternative pull-up forms in cmos vlsi, comparing nmos pull-ups and cmos inverters. analyze on/off states, open circuits, and how cmos achieves full 0 to vdd swings with low power.
CMOS inverter voltage transfer characters and its switching threshold point39:52
Analyze the CMOS inverter voltage transfer characteristics, detailing how NMOS and PMOS switch to produce v_out from v_in. Explore cutoff, linear, and saturation regions and the switching threshold.
Bicmos inverters18:28
Latch up in CMOS circuits11:13

mos layers and NMOS color encoding with STICK AND mask layout schems8:27
mos layers and CMOS color encoding with STICK and mask layout schems3:07
stick diagram rule set5:56
Nmos inverter schematic and stick diagram6:39
NAND schematic and stick diagrams1:34
operation of not nor or gates8:01
Explain how depletion‑mode transistors realize not, nor, and or gates in cmos vlsi design, detailing input conditions, on/off states, and the resulting outputs for nand and not/nor configurations.
Stick diagram for NOR and OR gate5:09
cmos inverter schematic and stick diagram6:16
CMOS NAND schematic and stick diagram6:20
CMOS NAND twisted stick diagram and other modified models of sticks for NAND6:21
CMOS NAND operation4:12
CMOS NORoperation and stick diagram10:45
Explore the CMOS NOR operation by analyzing pull-up and pull-down networks, deriving the output expression, and illustrating a stick diagram with pmos and nmos transistors.
why design rules needed?6:06
lambda based layout rules14:46
CMOS inverter and CMOS- NAND layouts9:42
CMOS- NOR layout1:51
Explore implementing a cmos nor layout from a stick diagram, detailing pull-up and pull-down transistors, polysilicon gates, and metal routing with substrate and lambda contacts.

sheet resistsnce5:48
sheet resistance applied to Mos transistors6:32
sheet resistance for depletion mode MOS inverter4:48
sheet resistance for CMOS inverter4:23
Area capacitance of layers and standard capacitance in different technologies16:52
some area capacitances9:50
multil layer area capacitance13:16
time delay in MOS circuits12:11
inverter pair delay using NMOS7:29
Analyze the charge and discharge delays in a two-inverter pair using NMOS, including load capacitance, pull-up and pull-down resistances, and the impact of depletion and enhancement devices on total delay.
CMOS inverter pair delay4:55
Rise time estimation delay7:02
Estimate cmos inverter rise and fall delays by modeling the transistor as a saturated current source charging a load capacitor, deriving both rise and fall times.
Fall time estimation dealy and relation b/w rise and fall time8:47
Driving of large capacitive loads4:20
cascaded of inverters13:18
cascaded of inverter for N-even and odd conditions4:49
Explore how cascading inverters affects total time delay for even and odd numbers of stages, including transitions and the role of load and gate capacitances.
condition of pair delay to cascaded inverters for NMOS8:12
Condition of pair delay for CMOS cascaded inverter11:44
super buffers3:20
Explore how super buffers reduce the asymmetric charging and discharging delays in cascaded inverters, offering faster, more balanced timing than conventional inverters in CMOS VLSI design.
super buffers in inverting mode8:40
Examine how inverting super buffers use depletion and enhancement mode transistors to charge a capacitor, producing zero volts output at five volts input and five volts at zero volts.
super buffers in non inverting mode5:44
what is scaling4:17
scaling for device parameters7:23

parity generator and its block diagram5:47
parity generator iin one-bit cell7:57
Design a one-bit parity generator cell for CMOS VLSI, using aa and a bar with previous parity pi minus one and pi minus one bar, and its truth table.
Implementation of Parity generator with Nmos and CMOS along with stick diagram9:31
What is Bus Arbitration logic and types of Bus arbitration logic?3:11
Bus arbitration logic ,truth table,logic expression,stick diagram, n-bit BAL23:28
Master the priority based bus arbitration logic with n-bit BAL design, its truth table, logic expressions, and stick diagrams, including input-output flow, select signals, and transistor-level insights.
Design of Multiplexers 2:1 and 4:1 with schematic and stick diagram11:48
design of 4 bit adder (Ripple carry adder)20:06
This lecture presents the design of a 4-bit ripple carry adder in cmos vlsi, deriving sum and carry expressions from truth tables and implementing with logic gates or two-to-one multiplexers.
design of 4 bit adder (Ripple carry adder) contd.,14:26
design of carry look ahead adder part-118:38
The lecture analyzes ripple carry adder delay, introduces carry generate and carry propagate concepts, and describes carry look-ahead precomputation to reduce propagation delay.
Design of carry look ahead adder with CMOS schematic diagram-part216:32

Requirements

Having an interest on basic electronics but not needed the any expertise.

Description

Learn how to master on VLSI system Design & SubSystems of Digital Circuits and designing of different circuits like combinational and sequential etc. In this course you will learn very large scale integration design course from scratch and also covered each and every details with step by step procedure. Now a days very large scale integration technology emerging or growing day by day. You cannot imagine without the Basic VLSI Design & SubSystems of Digital Circuits or even electronics and integrated circuits because usage of electronic gadgets now becoming a part in our daily routines. So we much depend on VLSI system Design & SubSystems of Digital Circuits to design like portable electronic gadgets and other gadgets for different purposes. The silicon-integrated circuitry make it possible to design of digital circuits which may be very complex and most economical in space, power requirements and cost, and potentially very fast The area, power and cost have made silicon the dominant fabrication technology for electronics in very wide ranging areas of application. Like digital signal processing, analog and digital communications as well as in video processing etc. Metal oxide semiconductor (MOS) related circuitry will meet requirements but still it is being researched by ongoing improvements and the research in fabrication such that other techniques are being majorly adapted with gallium arsenide technology, including the use of materials other than silicon for the production of integrated circuits. . So its needed to learn VLSI system Design & SubSystems of Digital Circuits for better growth particularly for electronics and computer related people. So those who want to settle in VLSI design field learning these concepts is essential .so start your journey with this course from now onwards.

In this course you may learn the behavior of MOS circuits in detail manner as well as you could get the better understanding after completion of this course.

The course covers these topics

Basic Electrical Properties of metal oxide semiconductor(MOS) and Bipolar and metal oxide semiconductor circuits

Current and voltage relationship and its characteristics

The Non-saturated region

Saturated region

Metal oxide semiconductor transistor transconductance and output conductance relationship.

The pass transistor

Inverter characteristics

Determination of pull up to pull down ration for an NMOS driven by another NMOS inverter.

Pull up to pull down ratio for an NMOS Inverter driven by another NMOS inverter using the pass transistor.

Complementary metal oxide semiconductor as inverter and its characteristics

Transconductance and output conductance

Alternative forms of pull ups

Bipolar and Complementary metal oxide semiconductor inverter circuits.

MOS layers and NMOS color encoding with STICK AND mask layout schemes

MOS layers and CMOS color encoding with STICK and mask layout schemes

Stick diagram rule set

Nmos inverter schematic and stick diagram

NAND schematic and stick diagrams

Operation of not nor or gates

Stick diagram for NOR and OR gate

Cmos inverter schematic and stick diagram

CMOS NAND schematic and stick diagram

CMOS NAND twisted stick diagram and other modified models of sticks for NAND.

CMOS NAND operation.

CMOS NOR operation and stick diagram

Why design rules needed?

lambda based layout rules

CMOS inverter and CMOS- NAND layouts

CMOS- NOR layout

Sheet resistance

Sheet resistance applied to Mos transistors

Sheet resistance for depletion mode MOS inverter

Sheet resistance for CMOS inverter

Area capacitance of layers and standard capacitance in different technologies

Some area capacitances

Multil layer area capacitance

Time delay in MOS circuits

Inverter pair delay using NMOS

CMOS inverter pair delay

Rise time estimation delay

Fall time estimation dealy and relation b/w rise and fall time

Driving of large capacitive loads

Cascaded of inverter for N-even and odd conditions

Condition of pair delay to cascaded inverters for NMOS

Condition of pair delay for CMOS cascaded inverter

What is Super buffers ?

Super buffers in inverting mode & non inverting mode

What is scaling & Scaling for device parameters

Parity generator and its block diagram &Parity generator iin one-bit cell

Implementation of Parity generator with Nmos and CMOS along with stick diagram

What is Bus Arbitration logic and types of Bus arbitration logic?

Bus arbitration logic ,truth table,logic expression,stick diagram, n-bit BAL

Design of Multiplexers 2:1 and 4:1 with schematic and stick diagram

Design of 4 bit adder (Ripple carry adder)

design of 4 bit adder (Ripple carry adder)

Design of carry look ahead adder with CMOS schematic diagram-part2

Feel free to ask any doubt while learning the course

Happy learning!

Skill Gems Education

PUDI V V S NARAYANA

Who this course is for:

* Any one who want to learn more on VLSI DESIGN aspects in much more deeper its for you!
* Intermediate or engineering and post graduate or even company employees also can learn the course for better growth

CMOS VLSI Design & Sub Systems of Digital Circuits

What you'll learn

Explore related topics

Course content

Basic Plannar process for making of Integrated Circuit (IC)8 lectures • 15min

Basic Electrical properties of MOS and BiCMOS circuits and its concepts15 lectures • 3hr 49min

MOS and BiCmos circuit design process (including stick diagrams and layouts)16 lectures • 1hr 45min

Basic circuits 0f CMOS Circuits & its scaling. of circuits (Delay,Rs,drivers )22 lectures • 2hr 54min

Subsystems10 lectures • 2hr 11min

Requirements

Description

Who this course is for: