What you'll learn
- Draw layout from scratch, i.e. right from tech files to metal layer
- Understand each and every mask level, through appropriate fabrication steps
- Get to know how physical design flow communicates with CMOS fabrication process
- This is how 2 different industries communicate
Requirements
- Basic terms of CMOS, NMOS, PMOS
- A brief summary of my existing course on 'Circuit design and SPICE simulations' will help, but can do even without that course
- A brief knowledge of my existing courses on physical design flow and static timing analysis will also help
Description
Physical designers and CMOS fabrication team communicates with each other, and this course says it 'How?'
While physical designers use all the outputs from experiments performed by fabrication department, this course will demonstrate the best of both worlds and connect them through exchange of certain files in certain format
This way, custom layout designers get to know an insight how does fabrication works, fabrication engineers get to know, how layout engineers uses their information. So this course is a place where both meet, talk and connect.
Also, the standard files needed to draw and simulate layout, are being taken, deduced and created from scratch and on the fly. This is, by far, the best way to understand layout, and I can promise you an exciting journey throughout this course
Course is structured to explain the CMOS packaging and fabrication steps in beginning, followed by software and files used to draw and simulate layout, and look into DRC rules.
Next, we will take a simple CMOS inverter and apply all concepts learned above. Finally, we will learn the 'Art of layout' using Euler's path. This is where you will solve complex functions and draw a layout out of it.
Welcome you all to my course and Happy Learning!!
See you in class!
Who this course is for:
- Anyone curious to know the inception of layout
- Anyone curious to know the software behind layout drawing
- Anyone who wants to know how chip designers talk with chip fabrication department
Instructor
- 4.2 Instructor Rating
- 13,229 Reviews
- 44,774 Students
- 40 Courses
Tips on order in which you need to learn VLSI and become a CHAMPION:
If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) “IR aware STA” and “Low power STA”
6) Analyzed STA engine behavior for design size up to 850 million instance count ACADEMIC
1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.
2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software
PUBLICATION
1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”
2) Concurrent + Distributed MMMC STA for 'N' views
3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit
4) Placement-aware ECO Methodology - No Slacking on Slack