Vivado Basics: Learn FPGA Design with a PCIe Project

Name: Vivado Basics: Learn FPGA Design with a PCIe Project
Rating: 3.6 (168 reviews)

Master FPGA Development with Vivado: Design Xilinx FPGAs from Scratch Using VHDL or Verilog

Created byOfer Keren

Last updated 8/2025

English

What you'll learn

Master the Vivado Design Suite: Learn how to install, navigate, and use Vivado for FPGA design, simulation, and debugging.
Design FPGA Projects from Scratch: Understand how to create and implement projects using Xilinx FPGAs, including block design and adding IP cores.
Simulate and Debug Designs: Gain hands-on experience simulating projects with Vivado and ModelSim, and debug them using tools like the Integrated Logic Analyzer
Develop Advanced Features: Learn to work with PCIe communication, AXI interfaces, and Zynq 7000 processors for real-world applications.
How to create Bit or Mcs file, and even uploading it to a development board!
How to open SDK project.
Axi-Bus, Streamed and Memory-mapped IP's and differences.
How to setup the PCIe root complex write a full communication to the Pcie end point and how to simulate the PCIe.
Adding ILA ,integrated logic analyzer, the strongest tool for real-time debug.

Course content

9 sections • 32 lectures • 7h 59m total length

Introduction and Overview of the course VIVADO Xilinx FPGA - Learn from the...2:41
In this lecture i will explain about the course content.
Downloading and installing Vivado 2019.1 Xilinx FPGA tool4:17
How to download and install Vivado 2019.1
Xilinx site might change during the time, i added links for the downloading section under Xilinx site.
Downloading and installing ModelSim simulation tool3:58
In this lecture you will learn how to download modelsim for students edition.

How to open a new project in VIVADO Xilinx FPGA tool10:31
This lecture will explain you how to use the vivado after starting new project. Walk you through the buttons and options of the vivado tool.
How to open an existing project in VIVADO Xilinx FPGA tool1:33
This lecture will explain you how to open existing project in vivado
How to open an example project in VIVADO Xilinx FPGA tool6:18
Xilinx added example projects so you can use them as a reference for your design, it will help you understand how to connect different IP cores together.
In this lecture will explain to you how to open Vivado example project.
How to add files to a project in VIVADO Xilinx FPGA tool9:27
This lecture will explain to you how to add existing files to the project
Adding Block design to the project in VIVADO Xilinx FPGA tool16:25
This lecture explain how to add a block design and connect it to out project
IP Cores and Opening Xilinx IP Example Design in VIVADO Xilinx FPGA tool12:38
This lecture will explain you what IP Cores are and how to open Xilinx IP example design
Language templates- Primitive Cores in VIVADO Xilinx FPGA tool8:12
This lecture will explain you what primitives are and how to add them to your design

Run Synthesis in VIVADO Xilinx FPGA tool8:24
In this lecture you will learn how to synthesize your design.
The synthesis running on the VHDL file in the vivado and check your logic for error and creating a full map of components(LUTS).
It is almost like compilation but for vhdl files in vivado tool.
The synthesis can also tell you how many LUTS u need for your project.
Run Implementation in VIVADO Xilinx FPGA tool3:22
In this lecture you will learn how to run Implementation and check the error and warnings logs.
The implementation is taking the project that you have created and fit it to the fpga that you choose.
This is like Place and route. So every fpga has different timing methods, this part of the tool will place the project as it should so the timing will be the best on your fpga.
Creating Constraints file in VIVADO Xilinx FPGA tool12:05
Constraints Wizard in VIVADO Xilinx FPGA tool5:28
In this lecture you will learn to create Constraints.
The constraints are set of orders that will be used for putting Vivado limits, but are not forcing the it.
When Vivado is running the implementation it will consider the constraints first but will not force itself to these limits.
If one of the limits can't be achieve, Vivado will warn you about it.
Language templates in VIVADO Xilinx FPGA tool3:19
In this lecture you will learn how to use language templates.
View RTL schematic in VIVADO Xilinx FPGA tool3:13
In this lecture you will learn how to see the RTL schematic.
Creating a Bit file in VIVADO Xilinx FPGA tool4:53
In this lecture you will learn how to create Bitstream file(.bit file).
The Bit file is used for programming the Fpga with your project. Note that the Bit file will be loaded through JTAG which is the programmer and after every shutdown of the FPGA that have been loaded with Bit file is deleted.
A Bit file is loading the FPGA with your project until you shutdown the power of the FPGA, If you want the FPGA to load with your project every time you need a FLASH memory and an MCS or Bin file(both of the created from the bit file so this lecture is a must to know) - in the next lecture.
Load Bit file to the FPGA in VIVADO Xilinx FPGA tool3:54
Creating Bin file or Mcs file through the VIVADO for Ultrascale or 7 series16:08
In this lecture you will learn how to generate a Bin and Mcs files from the Bit file Through the VIVADO, this method is right for Ultrascales and 7 series FPGAs.(for the ZYNQ process MCS file i am explaining at the SDK part at this course).
Mcs and Bin files are used for flash memory, so the FPGA can load itself after every shutdown from an outside flash memory.

running vivado simulation in VIVADO Xilinx FPGA tool4:26
The simulation tool helps designers check their VHDL code.
Even that inside FPGA we know we can have timing problems that cannot be solved with simulations, the simulator can give us a first clue of how to fix our problems and to fix our coding problems
In this lecture you will learn how to add your test bench file(simulation VHDL file) and how to run the Vivado simulator.
Modelsim Configuration in VIVADO Xilinx FPGA tool7:56
Modelsim is a third party tool for VHDL simulation, the strongest tool for simulation actually.
Using modelsim can make an easier life for the developer.
In this lecture you will learn how to configure Vivado so it will be able to run the Vivado project inside Modelsim simulator tool.
Running and using Modelsim simulator16:42
In this lecture you will learn how to run the Modelsim simulator from vivado.

Export Hardware - Creating HDF file in VIVADO Xilinx FPGA tool7:44
How to create hdf file for the zynq7000(the ps part on the fpga) which is the processing system.
We need the hdf file for the next lecture, and it will be used inside the sdk for loading the connection between the PL and the PS.
PL = programmable logic(fpga part) , PS = processing system(cpu inside the fpga)
Open SDK New Project and create mcs/bin file in SDK Xilinx FPGA tool23:13
How to open the SDK, the SDK is a tool for programming the cpu part (PS) inside the FPGA. Very similar to eclipse(for programmer)
We will learn how to open new project and how to use our previous lecture .hdf file from our project.
Generate MCS or Bin file and load it to the QSPI - Zynq7000 in SDK Xilinx FPGA14:12
In this lecture you will learn how to create MCS or Bin file for the ZYNQ7000 and how to load it, and i will show you how to run the hello world on a development board.

Creating ILA in VIVADO Xilinx FPGA tool23:58
In this lecture you will learn how to create ILA - integrated logic analyzer. The ILA is like Signal-Tap of Altera's FPGAs.
The ILA is good for checking your FPGA in real-time. The ILA is an inside core that can be connected in parallel to any place inside
Creating Bit File with .ltx files and Run the ILA for real-time debug in VIVADO11:30
In this lecture i will teach you how to run the ILA on the FPGA and debug your project in Real-Time!

Requirements

No Prior FPGA or Vivado Experience Needed: This course is designed for beginners and starts from the basics.
Basic Understanding of Digital Logic: Familiarity with concepts like logic gates, flip-flops, and binary arithmetic will be helpful but is not mandatory.
A Computer: Students need a computer capable of running Vivado Design Suite and ModelSim (Windows/Linux recommended).
Vivado Design Suite: Instructions for downloading and installing Vivado 2019.1 will be provided in the course.

Description

Master Vivado: FPGA Development from Scratch with PCIe Integration

This Vivado course teaches you how to use the Vivado Design Suite to develop Xilinx FPGAs, equipping you with skills in high demand at leading companies like Apple, Microsoft, Intel, Amazon, and Google. Whether you're a beginner or looking to expand your expertise, this course has you covered!

Why Learn Vivado?
FPGA development is one of the most rewarding and in-demand professions in the hardware industry. This course is designed to take you from installing Vivado to mastering its advanced features like PCIe and AXI interfaces.

What You’ll Learn:

Installing Vivado Design Suite (2019.1) and ModelSim.
Creating and simulating FPGA projects using Vivado and third-party tools.
Working with Xilinx IP cores, constraints, and synthesis.
Designing and debugging FPGA projects in real-time with ILA.
Building a full PCIe project with step-by-step guidance.

Key Highlights:

Over 30 lectures, lifetime access.
A 2.5-hour PCIe project to solidify your skills.
Subtitles available in 16 languages.
A 30-day money-back guarantee!

What Students Are Saying:

“Very informative and helpful. I learned so much!” – Umesh Kumar Sharma
“Great explanation of PCIe implementation and Vivado usage.” – Paul Burciu

By the end, you’ll be ready to design complex FPGA projects and confidently use Vivado in professional settings.

Join now and take the first step toward becoming an expert FPGA developer!

Who this course is for:

Beginners in FPGA Development: Ideal for those with no prior experience in FPGA design or the Vivado Design Suite.
Engineering Students: Perfect for students studying electronics, computer engineering, or related fields who want hands-on experience with FPGA tools.
Professionals in Hardware Design: A valuable resource for engineers looking to expand their skill set in FPGA development and advanced features like PCIe and AXI interfaces.
Hobbyists and Enthusiasts: Great for tech enthusiasts who want to learn FPGA design as a new hobby or to work on personal projects.
Advanced Learners: Suitable for experienced FPGA developers seeking to deepen their understanding of Vivado’s advanced tools and features.
This course is for anyone eager to learn FPGA design, whether to start a career, boost skills, or pursue a personal interest in cutting-edge hardware development. Let me know if you'd like to refine this further!

Vivado Basics: Learn FPGA Design with a PCIe Project

What you'll learn

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Course content

Introduction to the course3 lectures • 11min

Vivado start7 lectures • 1hr 5min

Vivado Synthesis, Implementation and bit file creation9 lectures • 1hr 1min

Simulation3 lectures • 29min

ZYNQ7000 Core and AXI interface2 lectures • 1hr 6min

XSDK intro3 lectures • 45min

ILA - Integrated Logic Analyzer2 lectures • 35min

Creating FULL Project with PCIe (end point and root)+ simulating the project2 lectures • 2hr 45min

Extra1 lecture • 2min

Requirements

Description

Who this course is for: