Video Processing with FPGA
What you'll learn
- Implement different Computer Vision algorithm for Video Processing
- Creating IP from the VIVADO High Level Synthesis
- IP integration and configuration with Xilinx VIVADO
- Xilinx SDK Application Development
- Migrating the OpenCV algorithm on XfOpenCV
- Simulating & Generating xfOpenCV codes in the VIVADO HLS
- Integrating TPG, VDMA and Writing application for this blocks
- Vitis HLS and OpenCV installation Session for 2020.2 or later
Requirements
- Basics of FPGA Design
- High Level Synthesis Basics
- PC with installed VIVADO, HLS and SDK [we will also show the steps for installation]
Description
This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IP from the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGA Device.
We have "Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm" on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement.
After Completing this course you will be able to:
Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLS
Integrating the HLS IP with Video Processing Pipeline with TPG and VDMA and Implementing on the FPGA Device.
Implementing the XfOpenCV [SDSoC] Library on HLS for Computer Vision
Migrating the OpenCV algorithm into XfOpenCV
Who this course is for:
- Electrical Engineering Enthusiast
- Computer Science Enthusiast
- FPGA Design Professional
- Enthusiast of FPGA Design
Instructor
- 3.6 Instructor Rating
- 1,366 Reviews
- 15,917 Students
- 12 Courses
Digitronix Nepal is an FPGA Design Company serving global customers since 2013. As of the initiative of "Democratizing FPGA Education all over the World", Digitronix Nepal has partnered with LogicTronix [FPGA Design and Machine Learning Company] for creating online learning courses and tutorials on "FPGA, VHDL/Verilog, Computer Vision & Video Processing, High Level Synthesis (HLS), MATLAB/System Generator, Machine Learning Acceleratio, SDAccel, SDSoC, Pynq Development, etc."
Digitronix Nepal believes that with the "Ultra Low Cost and FREE Courses" on FPGA Design, enthusiast from any country can learn and explore on the Field of FPGA Design and grab the global opportunities on FPGA Design, ASIC/VLSI Design and Machine Learning Acceleration.