Video Processing with FPGA
3.4 (41 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
408 students enrolled

Video Processing with FPGA

Implementing different Computer Vision Algorithm on FPGA with VIVADO High Level Synthesis, SDK & SDSoC
3.4 (41 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
408 students enrolled
Created by Digitronix Nepal
Last updated 3/2020
English
English [Auto-generated]
Current price: $86.99 Original price: $124.99 Discount: 30% off
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This course includes
  • 3.5 hours on-demand video
  • 4 articles
  • 23 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Implement different Computer Vision algorithm for Video Processing
  • Creating IP from the VIVADO High Level Synthesis
  • IP integration and configuration with Xilinx VIVADO
  • Xilinx SDK Application Development
  • Migrating the OpenCV algorithm on XfOpenCV
  • Simulating & Generating XfOpenCV codes in the VIVADO HLS
  • Integrating TPG, VDMA and Writing application for this blocks
Requirements
  • Basics of FPGA Design
  • High Level Synthesis Basics
  • PC with installed VIVADO, HLS and SDK [we will also show the steps for installation]
Description

This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IP from the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGA Device.

We have "Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm" on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement.

After Completing this course you will be able to:

  1. Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLS

  2. Integrating the HLS IP with Video Processing Pipeline with TPG and VDMA and Implementing on the FPGA Device.

  3. Implementing the XfOpenCV [SDSoC] Library on HLS for Computer Vision

  4. Migrating the OpenCV algorithm into XfOpenCV

Who this course is for:
  • Electrical Engineering Enthusiast
  • Computer Science Enthusiast
  • FPGA Design Professional
  • Enthusiast of FPGA Design
Course content
Expand all 25 lectures 03:41:02
+ Section 1_2 TPG,VDMA and Video Processing Platform Development
8 lectures 01:16:18

This session includes the basics of TPG [Test Pattern Generator] IP of Xilinx. This TPG IP is based on HLS and can generate test pattern of image in stream format.

TPG Overview
16:33

This session is "how to design Xilinx vivado project with TPG and Zynq Processing System", this session can be realized as TPG with Microblaze. The current version of TPG need to be configured from the Master Block as Processor, so need PS or Microblaze. We show all the steps for creating VIVADO IP block design with TPG , Zynq PS and other peripherals. By the end of this project, we generate the bitstream and export it to VIVADO SDK.

Lab 1 Part I: TPG Project Development LAB on VIVADO
19:38

This session includes the session of writing software application for TPG from the Zynq Processing System.

Lab 1 Part II: TPG Development [SDK Configuration with Zynq PS]
06:41

This Lecture is the "how to implement the TPG project on FPGA Board and Test the Project". We have shown up the demonstration of the project.

Demo: TPG Implementation on ZedBoard FPGA
04:57

Overview of Test Pattern Generator and the Video DMA IP. We have talked about the DMA basics, types of DMA and how VDMA works in this session.

Preview 13:54

This is the Lab Session on VDMA with TPG. In this session we design the IP block design in VIVADO IP integrator using the Lab 1 TPG Lab Source. This session completes after the bitstream generation of the project.

Lab 2 Part I: TPG & VDMA- VIVADO IP Block Design
07:18

This session is on writing the software application with VIVADO SDK for TPG and VDMA. We have attached the necessary sources with this lecture for the lab session. So, we explain about the process of writing application for VDMA for TPG based video pipeline project.

This session or SDK program is needed for most of video processing projects implemented on the Zynq FPGA platform.

Lab 2 Part II: TPG & VDMA- SDK Application Development
04:48

This Lecture is Test of TPG and VDMA Project on the ZedBoard FPGA.

Preview 02:29
+ Section 2_1 Sobel Edge Detection with FPGA
8 lectures 01:14:22

Introduction to OpenCV, Sobel Edge detection algorithm. The openCV functions are explained in this lecture including the Sobel Edge Detection algorithm.

Sobel Edge Detection-HLS & OpenCV Algorithm
16:47

This session has LAB session on VIVADO hls for Sobel Edge Algorithm, we have provided the sources of "sobel edge detection algorithm", which then synthesized, simulated and then exported as IP to VIVADO IP integrator.

Lab 1 Sobel IP Design on VIVADO HLS
19:16

This is LAB session on VIVADO IP integrator, where we integrate the Sobel Edge Algoithm IP generated/exported from VIVADO HLS with other blocks [Xilinx IP block and Digilent IP blocks]. This session is targeted for the Zybo FPGA device, while same design can be created for other Zynq Boards. We show the steps of placing the constraint , generating the project and implementing it on the Zybo FPGA Board.

Lab 2 VIVADO IP integration of Sobel Edge IP on Streaming Mode
23:09

This is the demonstration session of the "Sobel Edge Detection" project on the Zybo FPGA Board.

Sobel Edge Demonstration on Zybo FPGA
02:30

This is LAB session on real time sobel edge detection with Zybo Z7-10/20 FPGA. We have covered the VIVADO IP design and VIVADO SDK programming for the real time sobel edge detection on this LAB session.

Sobel Edge Detection with Zybo Z7-10-Lab Session
06:12
Sobel Edge Detection with Zybo Z7-10 [Demo]
01:19

This is LAB session on "how to design the sobel edge detection design with VIVADO tool" for streaming mode. In streaming mode, you dont need the Processing System on Block Design and you even dont need the VIVADO SDK program( Software Application on SDK).

Sobel Edge Detection streaming design Zybo Z7-10
00:31
Sobel Edge Detection with ZedBoard and FMC HDMI
04:38
+ Section 2_2 Dilation & Histogram Equalize implementation on HLS
1 lecture 09:13

This session is an Oveview of Histogram Equalize Algorithm and How to implement it on OpenCV and HLS, simulating the algorithm on HLS and generating the HLS IP for VIVADO IP integrator.

Histogram Equalize Overview
09:13
+ Section 3: Fast Corner & Harrish Corner Detection
3 lectures 34:41

This session is an overview of Fast Corner Algorithm, It's OpenCV example and the HLS implementation overview.

Fast Corner Detection Algorithm Overview
08:32

This session is on writing Fast Corner Algorithm on VIVADO HLS, Simulating it with Image and Exporting fast corner algorithm as IP to VIVADO IP Integrator.

Lab 31: Fast Corner Algorithm HLS Synthesis, C Simulation & Implementation
18:17

This session is Harrish Corner Overview and Lab Introduction Session. We also have included the HLS Lab sources of Harrish with this Lecture.

Harrish Corner Overview and Lab Intro
07:52
+ Porting xfOpenCV into HLS
1 lecture 01:55

This session is on how to port the xfOpenCV source or function into HLS.

Porting xfOpenCV Harrish Corner into HLS
01:55
+ Bonus Section
2 lectures 01:12

This session is bonus session with the Low Cost Coupon Code of other Next Level Courses after completing it. It also consists of what you can do on project's after completing this course, what next is included in this lecture [article].

What Next?
00:39

Reference Links and books for learning more deep on the HLS, VIVADO and SDSoC based FPGA Development.

Reference Links
00:33