Name: Xilinx VIVADO Beginner Course for FPGA Development in VHDL
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Created byDigitronix Nepal

Last updated 5/2019

English

What you'll learn

Idea of VHDL Programming , VIVADO Design Methodology and Designing/Implementing Design in Zynq FPGA-ZedBoard
Use fundamental VHDL constructs to create simple designs. Understanding the Conditional Statements in VHDL.
Design Simulation testbench on VHDL and simulating the designs.
Design with structural design methodology on VHDL.
Designing Decoder, Adder, Register and Counter in VHDL and Implementing in ZedBoard
Implementing State Machine in VHDL; Designing/Implementing Sequence Detector

Course content

11 sections • 25 lectures • 5h 3m total length

Introduction and Overview of VHDL19:44
VHDL (Very High Speed Integrated Circuit Hardware Description Language) is a type of HDL which is developed by IBM, Texas Instrument on the DoD Funding in 70's. TheVHDL has been standardized by IEEE in 1987. Initially VHDL is developed for Configuring Logic Arrays , PLD's while as the invention of FPGA, ASIC this HDL is highly preferred for re-configuring those Logic Gate Arrays.

VHDL has three major section on Programming which is Library, Entity and Architecture. The Library consists of library files as header file on C/C++, the library file define the functions called on the program. The Entity section define all the input and output ports which are going to used on program. And Finally the Architecture Section includes the implementation of any assignment or operation or functionality on VHDL Program.
For this course we have utilized the state of art design tool form Xilinx which is VIVADO while yo can use ISE Design Suit for learning VHDL Programming aside of VIVADO Design suit.
VHDL Data Types and Operators:Overview with How to create user defined data type15:20
•Data types defines a set of values that a variable can store along with a set of operations that can be performed on the variable.

•So Each variable, port or signal has to be defined on VHDL which is classified as Data Types declaration of variable. Example of Data Types on High Level Programming Language (C Programming Language) are Char, Float, int , double etc.

In VHDL there are different types of data types which can be listed as: bit, Std_logic, integer, real, type etc.

This Lecture covers all the data types of VHDL and how to create user defined data type (also called as Enumerated Data Types) in VHDL.
Section 1_0 How to Install Xilinx VIVADO and Get 30 day Evaluation License6:23
See the Video and Find the attachment for downloading, installing and Managing 30 day Evaluation license for VIVADO. However this course can be done with ISE Design suit, the interface of VIVADO only the different than ISE.
Section_1 Lab Nor Gate in VHDL with VIVADO on ZedBoard18:09
In this lecture we have designed the NOR Gate on HDL, this Nor gate can be implemented on any Series of FPGA supported by ISE or VIVADO. While we have Zynq Family of FPGA Board which is Zedboard so we have planned the constraint for Zeddboard and we are going to see the output on FPGA on another Session.
Nor Gate Implementation on ZedBoard FPGA (Optional)1:53
This is optional Lecture session actually demonstration of NOR Gate on ZedBoard FPGA. Actually you dont need Zeddboard and VIVADO for learning this course, if you have ISE and other boards that is also good but you have to have idea of constranting those board and the design flow of tool you are using.

Simulation Overview and Lab: Simulation of NAND Gate in VIVADO19:28
In this Session we have simulated the testbench written for NAND gate on VHDL. The VIVADO has powerful simulator intool which is VIVADO Simulator which can be used for Run Behavioural Simulation, Pre/Post synthesis Simulation and Pre/Post Implementation Simulation. We have introduced on this lecture about how to write a testbench on VHDL and how to run that testbench file on VIVADO Simulator for generating simulation Waveform.

Lecture: Conditional Statement in VHDL16:22
Conditional Statement are those statement on VHDL which checks the condition or boolean expression and execute the statement according to the condition. There are different conditional statement on VHDL which are "With Select", "When Else", "Case", "IF Else". This statements has own speciality and syntax which has been talked on the lecture.
Section 3_2 Lab 31 Decoder Design and Implementation on ZedBoard13:36
In this lecture or Lab 31 we have designed the decoder using when else and case statement. The 2:4 Decoder actually decodes or converts the 2 bit binary data into 4 bit binary format. For implementing 2:4 decoder and simulating it we need to know about the truth table of the logic circuit's.
Section 3_3 Lab 31 Decoder Demo0:59
This lecture is also optional, if you have Zynq device than you can implement your decoder 2:4 in to your board or you can escape the session. In this demo we have presented the providing two inputs form the switch of Zynq Device and getting output on the LED of Board. The Functionality of Decoder has been implemented on the Zynq Board (ZedBoard) in this lab demo.

Section 4_1 Combinational Circuit Design in VHDL19:50
Combinational Circuit are those circuit which takes some inputs and generated some continational output as logical combination. Example of combinational circuit are Logic Gates, Encoder, Decoder, Multiplexer, De-Multiplexer etc. This logic circuit takes the input checks some specific input state and determine the output on the output ports.
In this lecture we have talked on the combinational circuit basics how to use conditional statement on design of combinational circuit.
Section 4_2 Lab41 Half Adder Design and Implementation with VIVADO and Zynq14:36
Half adder is the type of combinational circuit, in this lab 41 we have designed the Half adder on VHDL in VIVADO Design suit and we proceed the step of implementing the design targeted for Zynq FPGA.
Half Adder Implementation on ZedBoard: Demo0:59

Section 5 Structural Design with VHDL with Lab on Designing Full Adder using Hal24:14
Structural design allow designer/programmer to reuse different modules which are created separately. With this design methodology "One single module can be used number of time, so the code reusability can be achieved. We are going to design Full Adder in this Section (another Lecture) by using Half Adder two times. The Half adder has been designed on the previous lab i.e lab 41.
Section 5 Lab 51 Structural Design Lab for Full Adder Demo1:20
The Design of Full Adder using Half Adder is the method of Structural Design in VHDL. This structural design methodology is highly used for architect complex projects in to small modules and finally integrating this modules.
For Structural Design there must be careful implementation of two section. In the same project we need to add the previous source (for now half adder) and recent added source module (Full Adder). Full Adder module must include component section which call the entity of Half Adder on Full Adder and after than there must have port mapping section this port mapping interface the Half adder port to the Full Adder Port. If there is no direct connection of half adder ports with full adder ports then there we need signal; signal is a wire or interconnection between one port of module to another module inside of the top module (Full Adder).

Section 6_1 Sequential Circuit Design in VHDL19:14
Sequential Circuits are those circuits whose values is not just dependent on present input only as in combinational circuit but on past sequence of inputs
It stores bits , also known as having state
Example of sequential circuit are: Counter, Flipflops , Register etc.
so sequential circuit utilizes the memory element on the logic implementation
Section 6_2 Lab 61 BCD Counter Design and Implementation17:54
In this Lab Session we have imlemented the Binary Coded Decmal (BCD Counter; a 4bit binary counter counts upto 1111 from 0000). This BCD counter utilizes the main clock of FPGA which is 100 MHz in ZedBoard or 50 Mhz of Spartan. That 100 Mhz of Clock has been prescaled (divide) in to 2.667 hz i.e .335 second. Actually 100 MHz of clock generate 10ns of time delay on each led change of BCD counter so the clock prescle to .335 second has been done which is human realiazable delay for led blinking.
The prescaled (divided) clock has been used by Counter Process which counts up the counter from 0000 to 1111. If the counter reach 1111 then the counter will automatically started from 0000.
BCD Counter Implementation on ZedBoard: Demo1:07

Section 7 FSM Design in VHDL Lab 71 Sequence Detector Design18:58
Finite State Machine is the Problem Solving Approach on Digital Design in which actually the problems has to converted into finite number of state. Each state checks the inputs and provides the output along with there might have some state change happen. FSM Implemented examples are Traffic Light Controller Design, Vending Machine Design, Car Security System Design etc.
We have used this FSM for Sequence Detector Design , actually this FSM implementation checks the input sequence; if the input sequence is 1011 then the detection output will blink else the machine checks the input sequence continuously.
In this Section we have attached the Reference Guide on " VHDL Programming", this reference guide is targeted for intermediate level of learner.

ALU Design (ALU Overview and 8 Bit ALU Design)-I15:52
This section is on Basics of Arithmetic and Logical Unit. We have presented the 2 bit ALU , 8 Bit ALU with Register and N bit ALU in this lecture.
ALU Design (ALU Overview and 8 Bit ALU Design)-II12:58
This Second section of ALU Design explains about the Register Declaration in VHDL, Generic Implementation and Creating Simulation Testbench for the 8 bit and N bit ALU.
ALU Design: Lab 81 N bit ALU Design20:22
Lab session on N bit ALU design and simulation with Xilinx VIVADO tool.

Requirements

Basic idea of VHDL
Idea of VIVADO Design Suit and Zynq 7000 Architecture
FPGA Design Methodology Basic
We have included all the basics of VHDL, VIVADO and Zynq in this Course, So No Worries!!!

Description

"Learn VIVADO Development from Basic to Intermediate Level!!!"

This Course is of VHDL Programming from Basic (logic gate design) to Advance Design (Structural Design and State Machine Design). After completing the course student will get idea of VHDL programming design methodology, VIVADO Design Flow, Zynq Architecture, Creating Simulation Testbench, Conditional Statements, Combinational Circuit Design with VHDl, Sequential Circuit Design, Structural Design in VHDL and State Machine Design in VHDL.

In each section we have included Lab session on VIVADO which have been implemented on Zynq Board (i.e ZedBoard) FPGA, so Student will get complete design skill on VHDL with VIVADO.

You guys can Learn the course while using ISE Design Suit.While VIVADO is successor of ISE so this Course and VHDL Design Methodology is same for ISE based design so do not scare about VIVADO because of it just a latest version of Design tool than ISE.

The Top Level Outlines of the Course is:

Basic Digital Design with VHDL and VIVADO Tool
Creating Testbench on VHDL and Simulating with VIVADO Tool
Combinational Circuit Design in VHDL: Decoder Design,
Sequential Circuit Design in VHDL: BCD Counter Design and implementation on ZedBoard
Implementing digital design lab on Xilinx Zynq Boards: ZedBoard and Zybo
Structural Design in VHDL: Creating Full Adder using Half Adder
State Machine Design : Designing Sequence Detector in VHDL
8-bit ALU Design and Simulation in VHDL

Who this course is for:

Electronics Engineering
Computer Science
Electrical Engineering
Robotics Enthusiast
Embedded System

What you'll learn

Explore related topics

Course content

Section 1_Introduction and Overview of VHDL, VIVADO & Zynq5 lectures • 1hr 1min

Simulating VHDL code with Testbench1 lecture • 19min

Conditional Statements in VHDL3 lectures • 31min

Section 4_A Combinational Circuit Design(Half Adder Design) with VHDL in VIVADO3 lectures • 35min

Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL1 lecture • 8min

Section 5 Structural Design with VHDL (Full Adder Design using Half Adder)2 lectures • 26min

Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL3 lectures • 38min

Section 7 Finite State Machine Design:Sequence Detector Design/Implement in VHDL1 lecture • 19min

ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm)3 lectures • 49min

VHDL Reference Guide (From Basic Design to FSM Examples) from Digitronix Nepal1 lecture • 15min

Requirements

Description

Who this course is for: