Learn VHDL Programming with Xilinx ISE & Spartan/Nexys FPGA
3.7 (13 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
186 students enrolled

Learn VHDL Programming with Xilinx ISE & Spartan/Nexys FPGA

In this 3.5 hour you will learn:Creating VHDL Design,Writing testbench for Simulation & Implementing Design on FPGA Kit.
3.7 (13 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
186 students enrolled
Created by Digitronix Nepal
Last updated 1/2019
English
Current price: $90.99 Original price: $129.99 Discount: 30% off
5 hours left at this price!
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This course includes
  • 3.5 hours on-demand video
  • 4 articles
  • 10 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Learn about VHDL Programming Methodology
  • VHDL Syntax and Semantics
  • Digital Logic Component Design with VHDL
  • Conditional Circuit Design with VHDL
  • Computational and Sequential Circuit Design with VHDL
  • Structural Design with VHDL
  • State Machine Design with VHDL
Requirements
  • Basic idea of Digital Design
  • Basic Idea of Programming Language
  • VHDL is started from the Beginning so no need to Worry about the prerequisites!
Description

Learn VHDL Programming with Xilinx ISE Design Suit and Spartan/Nexys FPGA.This Course covers from the basics of VHDL Syntax, VHDL Design Methodology, Basic Logic gate design with VHDL, Creating Simulation testbench on ISE , Simulating design, implementing design and testing/verifying functionality on FPGA.

In the third Section Course includes the conditional statement on VHDL, Creating Combinational and Sequential Circuit on VHDL, Structural Design in VHDL and State Machine Design in VHDL. We have Lab Session on each Section so you will be more familiar with labs or doing projects on VHDL with Xilinx ISE Design suit. We also have included the Uploading the Bit file to Spartan/Nexys FPGA and the Demonstration of the Output on the FPGA. 

We also have attached the "VHDL Programming Reference Guide Prepared by Digitronix Nepal" in the course. Meet You in the Course!!!

Who this course is for:
  • Electrical and Computer Engineering
  • Electronics Engineering
  • Computer Science
Course content
Expand all 20 lectures 03:48:01
+ Introduction
8 lectures 01:22:48

•Data types defines a set of values that a variable can store along with a set of operations that can be performed on the variable.

•So Each variable, port or signal has to be defined on VHDL which is classified as Data Types declaration of variable. Example of Data Types on High Level Programming Language (C Programming Language) are Char, Float, int , double etc.

In VHDL there are different types of data types which can be listed as: bit, Std_logic, integer, real, type etc.

This Lecture covers all the data types of VHDL and how to create user defined data type (also called as Enumerated Data Types) in VHDL.

Preview 15:20
Section 1 Lab 12 Implementation of NAND Gate on FPGA with ISE Impact
01:02

Demonstration of AND Gate on Nexys 2 FPGA (a family of Spartan 3e), The Projects and the necessary sources are attached with the lecture(demo).

(Optional) AND Gate Implementation on Nexys 2 FPGA (Demo)
01:18
VHDL Reference Guide from Digitronix Nepal: For Beginner to Intermediate Learner
15:30
+ Simulating VHDL Program with Testbench
1 lecture 19:57

This Section covers the Simulation Methodology on ISE Design Suit with VHDL. simulation is the process of creating virtual environment and manipulating the input variables for getting corresponding output. Creating simullation testbench in VHDL with ISE is simple and we are going to design and simulate NAND gate in this section.

Section 2 Simulation NAND Gate with VHDL and ISE Design Suit
19:57
+ Conditional Statement on VHDL (If else, Case, When Else and With Select)
1 lecture 19:03

There are different conditional statement on VHDL which can be differentiated as Sequential Statement ( If Else, Case, With Select, When Else) and Concurrent Statement (Process Statement). In this section we have brief overview on this statement and Creating Decoder with this conditional statement.

Section 3 Conditional Statement on VHDL_Design of Decoder
19:03
+ Section 4 Combinational Circuit Design with VHDL
3 lectures 48:28

Combinational Circuit are those logic circuit which takes input and process it as logical and operation and provides output. This combinational circuit doesnot consists of memory and it might not need to be clock sychrnized.

In this Section we have overview of combinaitonal circuit and types of its, examples of combination of gates, adder, comparator, multiplexer, and decoder.

Section 4_1 Combinational Circuit Design Overview
20:20

Design, Simulation and Implementation of Half Adder in VHDL with ISE Design Suit and Targeted for Spartan 3E and Nexys FPGA.

This is lab session , you will design Half adder in VHDL, create Testbench for simulation, write constraint and synthesize the design, implement the design and generate the programming file.

Section 4_2 Half Adder Design Simulation and Implementation on VHDL with ISE
19:55

Seven Segment Decoder Design in VHDL, Detail Reference Manual with VHDL Code.

Section 4_3 Seven Segment Decoder Design in VHDL & Implementation on Nexys FPGA
08:13
+ Section 5 Sequential Circuit Design with VHDL and ISE
2 lectures 19:35

Sequentual Circuit Design Overview, types of sequential circuit  as Flipflops, Register, counter has been briefed in this lecture. We also have talk on VHDL programming for those sequential circuit's and design methodologies for those circuits with clock triggered methodology.

We have to check Rising Edge of Clock for doing operation on sequential circuit , we have presented two method for checking rising edge on this lecture. 

Section 5 Sequential Circuit Design with VHDL and ISE
14:32

BCD Counter Design in VHDL and Generating Bit File from ISE Design Suit.

BCD Counter Design with VHDL and ISE
05:03
+ Section 6 Structural Design in VHDL: Creating Full Adder using Half Adder
3 lectures 37:26

Structural Design Overview: how to create different modules on same project, how to integrate them in the top module. The component declaration, Signal declaration and port mapping on Top Module has been explained in this section in detail.

Section 6 Structural Desgin in VHDL with ISE and Spartan_Nexys FPGA
14:53

In this lab you are going to design Half Adder initially and then that Half adder is going to used on Full Adder Module with Structural Design Methodology. For Structural Design Methodology you need to know about Component, Signals and Port Mapping which as been explained in this section clearly.

Join the Course! Happy Learning!

Section 62 Structural Design of Full Adder Design with Half Adder in VHDL/ISE
21:44

Demonstration of Full Adder Implementation on Spartan 3E Starter FPGA Kit. You can check the functionality of full adder on the demo as well as on your FPGA Board.

We will attach the Demo on Nexys 2 Soon.

Section 63 Full_adder_implementation_on_Spartan_3E_FPGA
00:49
+ Bonus Lecture
2 lectures 00:43

Books and Reference Links for more sharpening VHDL and knowing the Xilinx ISE Development.

Books and Reference Links
00:24
What Next?
00:18