VHDL Programming with Intel Quartus Prime Tool
- Basic of Digital Design & Logic Gates
This course covers the VHDL Programming Language from the basic to the intermediate level. We have presented basics of VHDL Language, its syntax/semantics, conditional statements, process statement with example project on Quartus prime tool. We also have Lab session on Combinatorial circuit design, sequential circuit design and state machine design.
This course also have sessions on writing the testbench module and simulating it with Modelsim. Another method of simulation and verification of VHDL design, Vector Waveform Generator is also presented in this course with Example.
Another Important part of this course is "Structural Design Methodology" in VHDL, we showed the design of "Full Adder" using the "Half Adder" module with Structural Design Method.
- Electrical Engineering
- Computer Science
- Introduction to VHDL and Overview of Quartus Prime Tool
- Simulation of NAND Gate with Quartus Prime & Modelsim
- Simulation of VHDL Design with Vector Waveform Generator: Overview
- Basic Logic Gate [AND+OR] Design & Simulation with VWF
- Conditional Statements in VHDL and Decoder Design Lab
- Combinatorial Circuit Design
- Structural Modeling: Design of Full adder using half adder
- Sequential Circuit Design in VHDL
- Finite State Machine Design
Digitronix Nepal is an FPGA Design Company. As of the initiative of "Democratizing FPGA Education all over the World", Digitronix Nepal have partnered with LogicTronix for creating online learning courses and tutorials on "FPGA, VHDL/Verilog, High Level Synthesis (HLS), MATLAB/System Generator, SDAccel, SDSoC, Pynq Development, etc."
Digitronix Nepal believes that with the "Ultra Low Cost and FREE Courses" on FPGA Design enthusiast from any country can learn and explore on the Field of FPGA Design and grab opportunities on this field.