What you'll learn

Learn VHDL Basics
Simply structured Course that anyone can understand
Get to learn all concepts of VHDL
Prepare for Competitive Exams of Electronics

Course content

9 sections • 31 lectures • 3h 59m total length

Introduction and terms used in VHDL9:47
Introduction to VHDL (VHSIC Hardware Description Language)
VHDL stands for Very High-Speed Integrated Circuit Hardware Description Language. It is a programming language used to model and simulate the behavior and structure of digital electronic systems such as FPGAs and ASICs.
VHDL is used in:
Digital circuit design and simulation
Synthesis into hardware (FPGA/ASIC)
Testbenches to verify digital designs
? Why Use VHDL?
Design complex digital systems
Simulate before implementation
Document designs clearly
Portability between tools and platforms
? VHDL Design Flow (Simple Steps)
Design Entry – Writing VHDL code
Simulation – Test the design with a testbench
Synthesis – Convert VHDL into gate-level netlist
Implementation – Place & route on FPGA
Programming – Load onto the hardware
Common Terms Used in VHDL
Term Description
Entity Describes the interface (inputs/outputs) of a circuit/module
Architecture Describes the internal behavior or structure of the entity
Signal Used to connect components or represent wires
Port Declared in an entity to define inputs and outputs
Process A sequential block used for describing behavior (uses if, case, etc.)
Component A reusable module that can be instantiated in another design
Library/Use Statements to include standard libraries (IEEE.STD_LOGIC_1164.ALL, etc.)
STD_LOGIC A 9-valued logic type (U, X, 0, 1, Z, W, L, H, -) used for digital signals
Testbench A VHDL file to test the functionality of a design (no ports, just simulation)
Concurrent VHDL code that executes in parallel (outside process)
Sequential VHDL code inside process, runs in order
Features of VHDL11:35
Writing an Entity In VHDL10:47
In VHDL, an entity defines the interface to a digital circuit or module — it tells us what goes in and what comes out, i.e., the inputs and outputs.
? Purpose of entity
Declares the name of the design unit
Lists ports (input/output signals)
No behavior is described here — only the structure visible from outside
Syntax of an entity
entity <entity_name> is
Port (
<port_name1> : in <data_type>;
<port_name2> : out <data_type>;
...
);
end <entity_name>;
How to write a simple Architecture?10:02
Simple Architecture in VHDL
In VHDL, the architecture describes what a circuit does — its behavior or structure. It is paired with an entity.
? Structure of an Architecture
architecture <architecture_name> of <entity_name> is
-- (optional) signal declarations
begin
-- concurrent or sequential statements
end <architecture_name>;

Example: AND Gate (Entity + Architecture)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- ENTITY: Interface
entity AND_Gate is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC
);
end AND_Gate;

-- ARCHITECTURE: Behavior
architecture Behavioral of AND_Gate is
begin
Y <= A AND B; -- simple concurrent assignment
end Behavioral;
Types of VHDL Modelling10:13
In VHDL (VHSIC Hardware Description Language), there are three primary types of modeling used to describe digital systems. Each type focuses on a different level of abstraction and is used based on design needs:
1. Behavioral Modeling
What it is: Describes what the system does, not how it's implemented.
Level of abstraction: High (algorithmic level).
Focus: Uses sequential statements inside processes to describe the functionality of the system.
Keywords/constructs used: process, if, case, loop, wait, variables, etc.
Example use case: Describing an ALU operation without worrying about the gates used.
process(A, B, Sel)
begin
case Sel is
when "00" => Y <= A + B;
when "01" => Y <= A - B;
when "10" => Y <= A and B;
when others => Y <= (others => '0');
end case;
end process;
2. Dataflow Modeling
What it is: Describes how data flows between different components using concurrent signal assignment.
Level of abstraction: Medium.
Focus: Based on boolean expressions and operators, useful for combinational logic.
Keywords/constructs used: Concurrent signal assignments (<=), with-select, when-else.
Example use case: Creating a multiplexer or basic logic gate combinations.
Y <= (A and B) or (C and D);

or using with-select:
with Sel select
Y <= A when "00",
B when "01",
C when "10",
D when others;

3. Structural Modeling
What it is: Describes a system by connecting components together (like a schematic).
Level of abstraction: Low (gate or module level).
Focus: Shows the interconnection of components (entities/architectures).
Keywords/constructs used: component, port map, signal.
Example use case: Building a 4-bit adder from 1-bit full adder components.
U1: full_adder port map(A => A(0), B => B(0), Cin => Cin, Sum => S(0), Cout => C1);
U2: full_adder port map(A => A(1), B => B(1), Cin => C1, Sum => S(1), Cout => C2);
-- and so on...

Summary Table:
Modeling Style Abstraction Description Focus Common Use
Behavioral High Functional behavior Algorithms, testbenches, FSMs
Dataflow Medium Signal flow & logic expressions Combinational logic
Structural Low Component interconnection Gate-level or block-level designs
Behavioral Modelling of AND Gate7:27
? Explanation:
process(A, B): Sensitive to changes in A or B.
Behavioral style: Uses an if statement to describe logic based on the functional behavior.
No mention of internal gates: Just what the circuit should do, not how it's built

Data Types In VHDL5:36
In VHDL, data types are crucial for describing the nature of signals, variables, and constants. VHDL provides a rich set of data types categorized into several groups.

? 1. Scalar Data Types
These represent single values.
a. Bit Types
Type Description
bit Two values: '0' and '1'
boolean Values: true, false
std_logic 9-value logic system (more realistic for digital logic simulations)
std_logic values:
Value Meaning
'U' Uninitialized
'X' Forcing Unknown
'0' Logic 0
'1' Logic 1
'Z' High Impedance
'W' Weak Unknown
'L' Weak 0
'H' Weak 1
'-' Don't care
b. Numeric Types
Type Description
integer Whole numbers (default range is implementation-defined)
natural Non-negative integers (subset of integer)
positive Positive integers (> 0)
real Floating-point numbers
time Used for simulation delays
? 2. Composite Data Types
Made of multiple values.
a. Array
Group of elements of the same type.
Common arrays:
bit_vector
std_logic_vector
signal A : std_logic_vector(3 downto 0); -- 4-bit vector
b. Record
Combines different types into one unit (like a struct in C).
type ALU_Output is record
result : std_logic_vector(3 downto 0);
zero : std_logic;
end record;
? 3. Access Type (Pointer-like)
Rarely used in basic hardware design.
Used for dynamic data structures.
type ptr is access integer;
? 4. Enumerated Type
User-defined types with symbolic values.
type State_Type is (Idle, Load, Execute, Done);
signal state : State_Type;
? 5. File Type
Used for file I/O operations in simulation.
file myFile : text open read_mode is "input.txt";
? Standard Libraries and Types

✅ Summary Table
Category Examples
Scalar bit, boolean, integer, real, std_logic
Composite array, record
Enumerated User-defined symbolic types
Access Pointer types
File For simulation file I/O
Operators In VHDL5:18
In VHDL, operators are symbols or keywords used to perform operations on data objects like signals, variables, or constants. These operators vary by data type and operation category.

? 1. Arithmetic Operators
Operator Description Example
+ Addition C <= A + B;
- Subtraction C <= A - B;
* Multiplication C <= A * B;
/ Division C <= A / B;
mod Modulo (remainder) R <= A mod B;
rem Remainder R <= A rem B;
** Exponentiation C <= A ** 2;
abs Absolute value C <= abs(A);

? Used with: integer, real, signed, unsigned

? 2. Relational (Comparison) Operators
Operator Description Example
= Equal if A = B then
/= Not equal if A /= B then
< Less than if A < B then
> Greater than if A > B then
<= Less than or equal if A <= B then
>= Greater than or equal if A >= B then

? Returns a boolean value.

? 3. Logical Operators
Operator Description Example
and Logical AND Y <= A and B;
or Logical OR Y <= A or B;
nand NOT AND Y <= A nand B;
nor NOT OR Y <= A nor B;
xor Exclusive OR Y <= A xor B;
xnor Exclusive NOR Y <= A xnor B;
not Logical NOT (unary) Y <= not A;

? Used with: bit, boolean, std_logic, std_logic_vector, etc.

? 4. Shift Operators (from numeric_std)
Operator Description
sll Shift Left Logical
srl Shift Right Logical
sla Shift Left Arithmetic
sra Shift Right Arithmetic
rol Rotate Left
ror Rotate Right

? Example:

Y <= A sll 2; -- shift left by 2 bits

? 5. Concatenation Operator
Operator Description Example
& Concatenation Z <= A & B;

? Combines vectors or bits.

? 6. Miscellaneous
Operator Description Example
' Attribute access A'length, clk'event
:= Variable assignment temp := A + B;
<= Signal assignment Y <= A and B;

With-Select Statement4:57
When- Else Statement4:14
Process Statement12:25
In VHDL, a process statement is used to describe sequential behavior within an architecture. It's a powerful way to model both combinational and sequential logic.
? Basic Syntax of a Process Statement
process (sensitivity_list)
begin
-- Sequential statements go here
end process;

? Example: Combinational Process (AND gate)
architecture Behavioral of AndGate is
begin
process(A, B)
begin
Y <= A and B;
end process;
end Behavioral;

Here, A and B are inputs, and Y is the output. The process is triggered whenever A or B changes.
? Example: Sequential Process (D Flip-Flop)
architecture Behavioral of DFlipFlop is
begin
process(Clk)
begin
if rising_edge(Clk) then
Q <= D;
end if;
end process;
end Behavioral;
This models a D Flip-Flop. The process is sensitive only to the clock (Clk), and updates output Q on the rising edge.
? Key Points about process:
Sequential Execution: Statements inside run sequentially, unlike concurrent statements outside.
Sensitivity List: Determines when the process "wakes up".
For combinational logic, include all inputs.
For clocked/sequential logic, usually just the clock and optionally a reset signal.
You can use if, case, loop, etc., inside a process.
✅ When to Use a process:
When you need sequential logic (like flip-flops).
When complex decision-making (if/case) is needed.
When creating FSMs (Finite State Machines).
IF LOOP7:08
In VHDL, there is no construct called if loop — however, it sounds like you're mixing up two valid constructs:
if → for conditional execution
loop (like for or while) → for repetition
But you can use an if inside a loop, or vice versa, depending on what you're trying to do.
✅ 1. Using if inside a loop
This is commonly done when you want to perform a conditional operation within a loop.
? Example: Setting the even bits of a vector to '1'
process
variable result : std_logic_vector(7 downto 0);
begin
for i in 0 to 7 loop
if (i mod 2 = 0) then
result(i) := '1';
else
result(i) := '0';
end if;
end loop;

-- Use result, e.g., assign to a signal
output <= result;
wait;
end process;
Summary
Goal Use
Condition-based execution if ... then
Repeating statements loop, for, while
Mix logic Nest if inside loop, or vice versa
FOR LOOP5:24
In VHDL, a for loop is used primarily inside processes, functions, or procedures for sequential execution during simulation or synthesis (mostly for generating repetitive hardware structures or initializing signals).
Syntax of a for loop in VHDL:
for variable in range loop
-- statements
end loop;

Example 1: Simple for loop in a process
process
variable i : integer;
begin
for i in 0 to 7 loop
-- Example: do something 8 times
report "Iteration " & integer'image(i);
end loop;
wait; -- to stop the process
end process;
While LOOP4:28
A while loop executes as long as the condition remains true. Unlike the for loop, where the number of iterations is fixed, the while loop continues dynamically based on a condition.

Syntax:
while condition loop
-- sequential statements
end loop;

Important Points:

The loop variable must be updated inside the loop to eventually make the condition false.

Avoid infinite loops — your condition must become false at some point.

Usually used in processes or subprograms (functions/procedures).

Often used for simulation or behavioral modeling, but less common in synthesis.

Example: Counting from 0 to 4 with while loop
process
variable i : integer := 0;
begin
while i < 5 loop
report "i = " & integer'image(i);
i := i + 1; -- important: update the variable to avoid infinite loop
end loop;
wait; -- to stop the process after loop ends
end process;

When to use while loop in VHDL?

When the number of iterations depends on some runtime condition.

For algorithmic or testbench code.

When you don’t know the iteration count beforehand.

Contrast with for loop:

for loop: fixed iteration count (great for synthesis).

while loop: dynamic condition (better for simulation or behavioral code).
CASE STATEMENT4:56
CASE Statement in VHDL

The case statement lets you choose one of many actions based on the value of a discrete expression (like an integer, std_logic, enumeration, etc.).

Syntax:
case expression is
when choice1 =>
-- statements
when choice2 =>
-- statements
when others =>
-- statements (default case)
end case;

Example: Simple 2-bit selector
signal sel : std_logic_vector(1 downto 0);
signal out : std_logic;

begin
process(sel)
begin
case sel is
when "00" =>
out <= '0';
when "01" =>
out <= '1';
when "10" =>
out <= '1';
when "11" =>
out <= '0';
when others =>
out <= '0'; -- default fallback
end case;
end process;

Key points:

The expression must be of a discrete type (integer, enumeration, or std_logic_vector).
The when others clause is required if you don’t cover all possible values (to avoid simulation errors).
Inside each when branch, you can put one or multiple sequential statements.
case statements are great for multiplexers, decoders, or any multi-choice logic.

Requirements

No specific Requirements, if you interested in Electronics that's more than enough

Description

VHDL (VHSIC Hardware Description Language) is a hardware description language commonly used for designing and simulating digital circuits. It is used in the design of FPGAs, ASICs, and other digital hardware. If you are a beginner and want to get started with VHDL, here are some basic concepts and code examples to help you get started:

It has several uses in the field of digital hardware design and development. Some of the key applications and uses of VHDL include:

Digital Circuit Design: VHDL is primarily used for designing digital circuits at various levels of abstraction, from high-level behavioral descriptions to low-level structural representations.
FPGA Programming: VHDL is commonly used for programming FPGAs (Field-Programmable Gate Arrays). FPGA programming allows engineers to implement custom digital circuits and prototypes on reconfigurable hardware.
ASIC Design: VHDL is used in the design and verification of Application-Specific Integrated Circuits (ASICs). ASICs are custom-designed integrated circuits for specific applications, such as in consumer electronics, automotive systems, and industrial applications.
Digital System Modeling: VHDL enables engineers to model complex digital systems and analyze their behavior before implementation. It helps in understanding and verifying system functionality.
Verification and Testing: VHDL is used to develop testbenches and test cases for verifying the correctness of digital designs. It allows engineers to simulate and validate designs against expected behavior.
Hardware Synthesis: VHDL can be synthesized into hardware descriptions (e.g., gate-level netlists) for implementation on physical devices like ASICs or FPGAs.
Intellectual Property (IP) Cores: VHDL designs can be packaged as reusable IP cores, allowing designers to integrate pre-designed functional blocks into larger systems.
Digital Signal Processing (DSP): VHDL can be used to implement DSP algorithms and functions in digital signal processing applications.
Prototyping and Rapid Iteration: VHDL allows for rapid prototyping and iteration during the development process, making it easier to refine and optimize designs.
Embedded Systems: VHDL is used to design and implement hardware components for embedded systems, such as microcontrollers and digital interfaces.
Aerospace and Defense: VHDL is prevalent in the aerospace and defense industries for designing and testing hardware used in critical applications like avionics and communication systems.

Overall, VHDL plays a crucial role in the design, verification, and implementation of digital hardware, making it a fundamental language in the field of digital design engineering. It provides engineers with a standardized and structured approach to describe and simulate complex digital systems.

Who this course is for:

This is for all Aspirants of core companies
To anyone interested in VHDL

What you'll learn

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Course content

Introduction6 lectures • 1hr

VHDL Data Types and Operators2 lectures • 11min

Statements used in VHDL7 lectures • 44min

VHDL Behavioral Coding - Basic Gates5 lectures • 26min

Behavioral Coding- Latches, Flip Flops3 lectures • 16min

Combinational Elements5 lectures • 29min

Introduction to Xilinx IDE and ISIM Simulator2 lectures • 32min

Interview Preparation Videos1 lecture • 23min

VHDL Quizzes0

Requirements

Description

Who this course is for: