VHDL Programming and Functional Verification

Explore combinational logic through truth tables and basic gates: not, and, or, xor, nand, nor, with algebraic expressions and gate symbols.

Explore combinational logic circuits including multiplexers, decoders, and encoders, and analyze half and full adders, ripple carry adders, and carry lookahead adders with generate and propagate signals.

Explore propagation and contamination delays, setup and hold times, hazards and metastability in flip-flops, and techniques to minimize clock skew and glitches in digital circuits.

Compare fine-grained and coarse-grained FPGA architectures, where fine-grained cells implement simple logic gates and flip-flops, and coarse-grained cells handle multi-variable functions and multi-bit storage, trading area for functionality.

Examine flexibility, efficiency, and trade-offs in hardware design and decide when algorithms suit a given architecture, while comparing general-purpose and dedicated architectures and outlining a virtual model.

Design an rtl model by mapping architecture to vhdl entities, confining critical paths, and using off-the-shelf subtests. Identify registers, combination clouds, state machines, and a clock-cycle schedule to guide coding.

Compare hardware description languages across design stages from algorithmic model to post-layout netlists, detailing purposes, abstraction levels, timing constraints, and languages like Python, MATLAB, C, and VDL.

declare a VHDL entity, name it, and declare its port with three inputs and one output, using in/out directions and a steady logic type.

Use selected signal assignments in VHDL to implement multiplexing. Learn how a selecting expression controls value assignment to signals with when clauses.

Describe the nine signal value types, including zero, one, x, h, l, w, z, and dash for don't care, and map each type to its corresponding value.

Explore VHDL operators, including inversion, bitwise and logical operations, string concatenation, arithmetic operations (absolute value, add, subtract, multiply, divide, modulo, exponentiation), and comparison and shift operators.

VHDL variables are local to one process and must be declared before the process body; inside the process, use assignments to the variable, often driven by a select signal.

Learn how to implement VHDL for loops by naming the loop, declaring a 0 to 15 range, and ending with end loop and the loop name.

Discover how procedures in VHDL enable reusing code across a model by defining ports, timing and control, and internal variables, then implement looping logic with a for loop.

Describe a state machine using state tables listing next state and output for each present state and input, and depict it with a state graph of vertices and directed transitions.

Compare synchronous and asynchronous contours and explain clocked behavior. Define flip-flop requirements, build a state table, derive D inputs, and illustrate counters to four, six, eight, and seven with reset.

Identify functional verification as a design step by comparing the original algorithm's functionality with the implemented digital circuits during simulation.

Declare an example test bench by defining an empty entity after library imports, name the empty entity other_TTB_TV (TV for test), declare only the entity, and end it.

Explore a VHDL test bench defining input and output signals, clock, reset, operands, and rounding mode, with six signals for each output and its expected result (overflow, exact, and result).

Set up the standard simulation for a device under test in VLSI design, using a random stimulus generator and a golden model to compare expected and required responses.

Set up a cpu simulation to verify a hardware design by converting C code to machine code, applying it to the cpu model, and compare results with the golden model.