VHDL Programming and Functional Verification

Explore number systems and binary arithmetic, converting binary to decimal and using hexadecimal base 16 for easier handling. Compare signed binary representations: sign-magnitude and two's complement.

Explore combinational logic through truth tables and basic gates: not, and, or, xor, nand, nor, with algebraic expressions and gate symbols.

Explore combinational logic circuits including multiplexers, decoders, and encoders, and analyze half and full adders, ripple carry adders, and carry lookahead adders with generate and propagate signals.

Master sequential logic circuits through flip flops—sr, d, jk, and t toggle—clock-edge behavior, and memory elements such as registers, shift registers, and ram, rom, sram, and dram.

Explore propagation and contamination delays, setup and hold times, hazards and metastability in flip-flops, and techniques to minimize clock skew and glitches in digital circuits.

Explore the top level FPGA architecture, including configurable input/output blocks, logic slices, and switch boxes, with examples of logic cells and digital signal processing slices.

Compare fine-grained and coarse-grained FPGA architectures, where fine-grained cells implement simple logic gates and flip-flops, and coarse-grained cells handle multi-variable functions and multi-bit storage, trading area for functionality.

Examine flexibility, efficiency, and trade-offs in hardware design and decide when algorithms suit a given architecture, while comparing general-purpose and dedicated architectures and outlining a virtual model.

Explore the flexibility versus efficiency trade-off across architectures, from hardwired ASICs to FPGAs and general purpose processors, and learn the principle of segregation for optimal hardware and programmable subsystems.

Evaluate whether your algorithm suits a dedicated VLSI architecture by applying criteria such as loose coupling, simple control flow, regular dataflow, finite-precision compatibility, and a true bit-level model.

Assemble general-purpose and dedicated VLSI architectures to balance computational efficiency and flexibility, using pipelined and bus-based designs where specialized units cooperate with a programmable processor.

Design dedicated vlsi architectures by moving from system-level specifications through behavioral modeling to structural rtl and gate-level verification, then prepare for back-end layout with automated scripts.

Design an rtl model by mapping architecture to vhdl entities, confining critical paths, and using off-the-shelf subtests. Identify registers, combination clouds, state machines, and a clock-cycle schedule to guide coding.

Compare hardware description languages across design stages from algorithmic model to post-layout netlists, detailing purposes, abstraction levels, timing constraints, and languages like Python, MATLAB, C, and VDL.

declare a VHDL entity, name it, and declare its port with three inputs and one output, using in/out directions and a steady logic type.

Explore how to declare a VHDL architecture by declaring an entity, then naming the architecture. Declare signals, begin the architecture, assign signals, and end the architecture.

Use selected signal assignments in VHDL to implement multiplexing. Learn how a selecting expression controls value assignment to signals with when clauses.

Describe the nine signal value types, including zero, one, x, h, l, w, z, and dash for don't care, and map each type to its corresponding value.

Explore VHDL operators, including inversion, bitwise and logical operations, string concatenation, arithmetic operations (absolute value, add, subtract, multiply, divide, modulo, exponentiation), and comparison and shift operators.

React when an event occurs on signals in its sensitivity list, such as A, B, or C, with wake up signals listed in parentheses after the process.

Declare registers to store input signal values and update their state on rising clock edges. Implement a reset to zero and an enable signal to control when the register updates.

VHDL variables are local to one process and must be declared before the process body; inside the process, use assignments to the variable, often driven by a select signal.

Describe delay modelling by scheduling a transaction on the output after a propagation delay TPD when inputs A or B change. Account for contamination delay by using another after clause.

Learn how to implement VHDL for loops by naming the loop, declaring a 0 to 15 range, and ending with end loop and the loop name.

Explore generics in VDL to store static time invariants and disseminate timing details like propagation and contamination delays to design entities, with constant statements instantiating generics at top of code.

Explore VHDL generate statements to build a grid of cell processes for the game of life, parameterized by rules, neighbors, and previous states.

Discover how procedures in VHDL enable reusing code across a model by defining ports, timing and control, and internal variables, then implement looping logic with a for loop.

Learn how VHDL functions differ from procedures, returning a single value and exhibiting combinatorial behavior with input arguments only, with no delay, event control, or inout or output arguments.

Explore the concept of finite state machines, why they are needed, the different types, and conclude with a practical implementation example.

Explore media machines, more machines, and Medvedev machines, where output rules differ: media machines use state and input, more machines use state only, and Medvedev machines output equals the state.

Describe a state machine using state tables listing next state and output for each present state and input, and depict it with a state graph of vertices and directed transitions.

Define the finite state machine states, build the state table and draw the state diagram, then code it as three concurrent processes: present-state, next-state, and output.

Compare synchronous and asynchronous contours and explain clocked behavior. Define flip-flop requirements, build a state table, derive D inputs, and illustrate counters to four, six, eight, and seven with reset.

Identify functional verification as a design step by comparing the original algorithm's functionality with the implemented digital circuits during simulation.

Explore two approaches to designing valid specifications: formal specifications with truth tables, state graphs, and state charts. Also use virtual prototypes that emulate functionality via software or FPGA devices.

Apply formal methods to capture the specification with equations and state charts, develop a virtual prototype, share for broad feedback, and refine it into the golden model for design.

A test bench simulates the design by applying stimulus vectors, including resets, driving a stoppable clock, and comparing actual outputs to expected responses to generate an ascii report.

Learn how to place library imports at the top of a VHDL test bench and walk through lines, including standard libraries, text i/o, numeric types, and a project union package.

Declare an example test bench by defining an empty entity after library imports, name the empty entity other_TTB_TV (TV for test), declare only the entity, and end it.

Explore a VHDL test bench defining input and output signals, clock, reset, operands, and rounding mode, with six signals for each output and its expected result (overflow, exact, and result).

Explore how a VHDL test bench declares signals, constants, and components, then implements a clock process that toggles high and low periods and stops at end of simulation.

Explore the example testbench for the 1 expected response process in VHDL, defining output variables, reading expected results from a file, and generating comparison reports to verify device behavior.

Set up the standard simulation for a device under test in VLSI design, using a random stimulus generator and a golden model to compare expected and required responses.

Set up a cpu simulation to verify a hardware design by converting C code to machine code, applying it to the cpu model, and compare results with the golden model.