VHDL for an FPGA Engineer with Vivado Design Suite

Name: VHDL for an FPGA Engineer with Vivado Design Suite
Rating: 4.5 (145 reviews)

Using Xilinx FPGA's

(145 ratings)

1,029 students

Created by Kumar Khandagle

Last updated 5/2022

English

English [Auto]

What you'll learn

Fundamentals of VHDL Programming that will help to ace RTL Engineer Job Interviews.
Understand Vivado Design Suite flow for Digital System Design.
How to write an RTL for Synthesis
Different Modelling Styles in Hardware Description Language , Concurrent and Sequential Statements in VHDL
How to use Xilinx IP's and create Custom IP's.
IP integrator Design flow of the Vivado.
Writing VHDL Test benches.
Hardware Debugging in Vivado viz. Integrated Logic Analyzer, Virtual I/O.
From Zero to Hero in VHDL

Requirements

Fundamental of Digital Circuit will give an added advantages.

Description

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the VHDL language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain. Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

Who this course is for:

VLSI Job Seeker/ Graduate student looking to pursue career as RTL Engineer/ Design Engineer/ Verification Engineer.
Anyone interested to learn Xilinx FPGA/ Vivado Design Suite/ VHDL Hardware Description Language
Anyone interested to start career in ASIC/ VLSI domain.

Kumar Khandagle

FPGA Developer Lead @ FinTech

4.5 Instructor Rating
3,366 Reviews
12,239 Students
22 Courses

I am working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards. Before Joining Fintech, I spent three years as a VLSI Trainer at Mumbai University, India, and one year as Research Scientist at the Prominent R&D Centre for Applied Electronic Research of India contributing to the development of Gradient Controller,64 Mhz Receiver on FPGA for Indigenous MRI Machine. During my free time, I love to develop Udemy Courses. I also collaborated with Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.