VHDL for an FPGA Engineer with Vivado Design Suite

Name: VHDL for an FPGA Engineer with Vivado Design Suite
Rating: 4.5 (291 reviews)

Using Xilinx FPGA's

Created byKumar Khandagle

Last updated 6/2023

English

What you'll learn

Fundamentals of VHDL Programming that will help to ace RTL Engineer Job Interviews.
Understand Vivado Design Suite flow for Digital System Design.
How to write an RTL for Synthesis
Different Modelling Styles in Hardware Description Language , Concurrent and Sequential Statements in VHDL
How to use Xilinx IP's and create Custom IP's.
IP integrator Design flow of the Vivado.
Writing VHDL Test benches.
Hardware Debugging in Vivado viz. Integrated Logic Analyzer, Virtual I/O.
From Zero to Hero in VHDL

Course content

19 sections • 180 lectures • 19h 43m total length

Agenda0:30
Read this before downloading newer version of Vivado : 2020.2 or higher0:03
How to Download, Install Vivado Design suite and add License.9:45
Xilinx Vivado Webpack LIC FILE
How to verify License Installation3:45
Adding boards such as Nexys 4 DDR which are not available in the Vivado3:39
Common Error with Vivado: Incorrect Microsoft Visual C++ redistributable package0:17

Agenda0:54
Demonstration of Parallel architecture usage4:54
Ease of working with FPGA's6:41
User Programmable I/O of FPGA vs MCU0:51
Comparing Temporary storage3:33
Whether Coding Guidlines really matters?9:24
How to buy FPGA board in India (without paying Custom duty and GSTN no.)4:36
Find affordable ways for individuals to buy FPGA boards in India without custom duty or GST, comparing Fighters Electronics, Element14, and Mouser Electronics.

Agenda0:57
Design Flow P17:04
Design Flow P29:12
Design Flow P314:23
Design flow P48:02
Design Flow P58:48
Summary of Design Flow9:03
First Look at VHDL Code16:51
Insights P16:31
Explore how to use the Vivado Design Suite’s documentation navigator, videos, knowledge base, and learning center to quickly access device family guidance, IP repository, and example projects.
Insights P24:08
Use of RTL analysis0:23
Use of Post-Synthesis View0:11
Assignment 1

Agenda1:55
Explore the fundamentals of signal and variable in VHDL, covering usage, data types, rate handling, and initialization to establish modeling foundations.
Fundamentals Signal and Variable P111:28
Compare signals and variables in VHDL to manage value reuse and scope. Signals are visible to all processes in an architecture, while variables stay local to a single process.
Fundamentals Signal and Variable P23:52
Format of Signal and Variable3:46
Datatypes in VHDL1:58
Using Built-in datatype7:49
Using Non-builtin datatypes3:30
Using User defined datatypes2:27
Using Signal9:50
Using Variable7:04
Initialization of Variable6:23

Agenda3:01
Different Modeling Style16:10
Dataflow Modeling Style Fundamentals4:20
Operators in Dataflow Modeling Style6:03
Assignment Operator in Dataflow Modeling Style3:59
Implementation of Half adder6:14
Implementation of Full adder9:59
Handling Multibit vectors P16:29
Handling Multibit vectors P23:09
Shift Operators Fundamentals14:33
Shift Operator Demonstration11:39
Explore how to use the numeric_std library to perform left and right logical shifts, as well as rotate and automatic shifts on unsigned vectors in VHDL, with practical simulation steps.
Rotation Operator Fundamentals3:24
Rotation Operator Demonstration5:55
Arithmetic Operator Fundamentals7:44
Arithmetic Opertation : Unsigned Type8:16
Arithmetic Opertation : Std_logic_Vector Type8:33
Explore arithmetic with std_logic_vector in vhdl, including addition, subtraction, and multiplication, with proper carry out, width extension via concatenation, and the standard_logic_unsigned library for two's complement results.
Understanding type-conversion function11:12
type-conversion Demonstration8:22
Conditional and Selected Signal Statement4:55
Compare conditional and selected signal statements in VHDL, highlighting priority evaluation versus parallel condition checks, with mux-based synthesis leading to identical FPGA implementation.
Conditional and Selected Signal Statement12:21
Implement Half Subtractor using Dataflow modeling style.
Implement 4:1 Mux with Dataflow Modeling Style
Implement 4-bit Gray to Binary Code Converter
Performing Division

Agenda0:58
Understand behavioral models and the skeleton of a process-oriented modeling strategy. Explore the fundamental constructs and an operator, and learn best practices to avoid SPG architecture mistakes.
Understanding Process block6:04
Behavioral Modeling Style Skeleton6:46
Understanding IF ELSE P16:10
Understanding IF ELSE P28:06
Good Practices : IF ELSE P13:59
Good Practices : IF ELSE P23:27
D-Flipflop with Synchronus Reset6:59
D-Flipflop with Asynchronus Reset2:35
Simulation : Asynchronus Reset D-Flipflop3:08
Simulation : Synchronus Reset D-Flipflop2:57
Case Statement Skeleton1:34
4:1 Mux with Case Statement4:21
Binary to Seven Segment Decoder P17:18
Binary to Seven Segment Decoder P211:09
Binary to Seven Segment Decoder P30:48
Implementing Counter11:13
Code0:22
Right Circular Shifter P16:33
Right Circular Shifter P212:27
Code0:33
Design 8:1 Mux with Behavioral Modeling Style
Design 8:3 Priority Encoder
Design Universal Circular Shifter

Requirements

Fundamental of Digital Circuit will give an added advantages.

Description

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the VHDL language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain. Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

Who this course is for:

VLSI Job Seeker/ Graduate student looking to pursue career as RTL Engineer/ Design Engineer/ Verification Engineer.
Anyone interested to learn Xilinx FPGA/ Vivado Design Suite/ VHDL Hardware Description Language
Anyone interested to start career in ASIC/ VLSI domain.

VHDL for an FPGA Engineer with Vivado Design Suite

What you'll learn

Explore related topics

Course content

Installing Vivado7 lectures • 18min

Performance Comparison ( Motivation)7 lectures • 31min

Frequently Asked Questions1 lecture • 1min

Vivado Design Flow P112 lectures • 1hr 26min

Vivado Design Flow Part 212 lectures • 54min

Fundamentals : Signal and Variable11 lectures • 1hr

Dataflow Modeling Style20 lectures • 2hr 36min

Behavioral Modeling Style21 lectures • 1hr 47min

Understanding Testbench12 lectures • 1hr 10min

Structural Modeling Style7 lectures • 53min

Requirements

Description

Who this course is for: