Learn VHDL Design using Xilinx Zynq-7000 ARM/FPGA SoC
3.8 (125 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
5,373 students enrolled

Learn VHDL Design using Xilinx Zynq-7000 ARM/FPGA SoC

For both the beginner and experienced Engineer using Vivado on the Zybo Z7 Xilinx Zynq FPGA Development Board
3.8 (125 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
5,373 students enrolled
Last updated 3/2020
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Current price: $139.99 Original price: $199.99 Discount: 30% off
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This course includes
  • 5 hours on-demand video
  • 7 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Describe and explain VHDL syntax and semantics
  • Create synthesizable designs using VHDL
  • Use Xilinx FPGA development board for hand-on experience
  • Design simple and practical test benches in VHDL
  • Use the Xilinx Vivado toolset
  • Design and develop VHDL models
Requirements
  • Familiarity with digital logic design, electrical engineering, or equivalent experience
Description

  Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA, ASIC, and VLSI digital systems. Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications. 

  At the end of this course, participants will be able to accomplish the following: 

  • Describe and explain VHDL syntax and semantics

  • Create synthesizable designs using VHDL

  • Use Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board for hand-on experience

  • Use the Xilinx Vivado toolset

  • Design simple and practical test-benches in VHDL

  • Design and develop VHDL models

  Prerequisites: 

  • Familiarity with digital logic design, electrical engineering, or equivalent experience.

  Even if you're now already familiar with VHDL but you've: 

  • Never used an attribute other than ‘event?

  • Never used variables?

  • Always used a process where a single concurrent statement would have sufficed?

  • Never used assert or report statements except (maybe) in a test-bench?

  • Never used an unconstrained vector or array?

  • Never used a passive process inside of an entity?

  • Never used a real or the math_real library package in synthesizable code?

  • Always used a single process per signal assignment?

  then this course will definitely have something for you as well.  You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable. 

Who this course is for:
  • Engineers
  • Hobbyists
  • Makers
  • Engineering Students
  • Engineering Managers
Course content
Expand all 34 lectures 05:13:41
+ Basics
6 lectures 37:45
Design Units
04:45
Comments
01:59
Literals
05:26
Xilinx Software Tool Installation
17:06
Quiz 1
5 questions
+ Data types & operations
5 lectures 48:39
Data Object Classes
07:09
Operators
04:44
Xilinx Zybo Z7 Xor Demo
11:30
Quiz 2
5 questions
+ Concurrent statements
3 lectures 30:29
Design Units
11:10
Concurrent Statements
11:09
Demo 2
08:10
Quiz 3
5 questions
+ Sequential statements
5 lectures 24:17
Sequential Statements
01:00
Wait Statements
02:26
Conditional Statements
10:26
Assert & Report Statements
05:36
Quiz 4
5 questions
+ Processes
4 lectures 50:49
Test Benches
03:22
Processes
20:40
State Machines
13:08
Quiz 5
5 questions
BasicFSM Demo
13:39
+ Subprograms
2 lectures 21:52
Procedures
07:35
Quiz 6
5 questions
+ Packages
2 lectures 20:05
Packages, Components, and Configuration
09:46
Quiz 7
5 questions
ColorFSM Demo
10:19
+ Design for synthesis
1 lecture 09:06
Design for Synthesis & Demo
09:06
+ Advanced topics
4 lectures 40:39
Life Demo
27:00
Aliases
06:47
Generics
03:56
Generate Statements
02:56
Quiz 9
5 questions