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Learn MoreVerilog on Intel (Altera) FPGA
Rating: 4.2 out of 54.2(67 ratings)
430 students
What you'll learn
- Verilog basic knowledge
- Verilog coding skill
- How to use intel FPGA tools, such as Quartus, Modelsim, USB Blaster etc.
- Drive all kinds of sensors
Explore related topics
Course content
6 sections • 96 lectures • 21h 1m total length
- Compile Environment Setup---Quartus & ModelSim10:07
For anyone who needs the compile software, you can download it directly from the following linker:
(1) cyclone-19.1.0.670.qdz ---
https://drive.google.com/file/d/1wPpb99pMdV6mKIYU8QijaW0ztcmBj_YA/view?usp=sharing
(2) ModelSimSetup-19.1.0.670-windows.exe ---
https://drive.google.com/file/d/1iTCKc_J5vsBFA7wHX6euhM-SLHdEYXb3/view?usp=sharing
(3) QuartusLiteSetup-19.1.0.670-windows.exe ---
https://drive.google.com/file/d/15xcpywAm4xer4DumYOJ-mjJLupHIZZVJ/view?usp=sharing
- Simplest LED “Hello, World!”15:59
- Simplest Testbench16:48
- ModelSim16:32
Learn how to set up and simulate Verilog on Intel FPGA using ModelSim on Windows: create a project, add sources, compile, fix errors, build a test bench, and view waveforms.
- USB Blaster26:43
Learn how to install the USB Blaster driver, connect the Intel FPGA, configure pins and a Quartus project, and program the board using the USB Blaster.
- Clock Divider 01 – Analysis & Coding22:12
Learn to implement a Verilog clock divider on an Intel FPGA by counting input cycles to produce a slower clock from 50 MHz to 100–400 kHz, with reset handling.
- Clock Divider 02 – Simulation34:03
- Clock Divider 03 – PLL IP27:47
- FIFO 01 – Introduction11:16
Explore the fifo, a first-in, first-out data structure with write and read pointers. Learn how full and empty signals, write/read enables, and clocking enables fast data transfer in FPGA designs.
- FIFO 02 – Synchronous FIFO 01: Analysis8:14
- FIFO 03 – Synchronous FIFO 02: Coding26:06
Implement a synchronous fifo with write and read processes driven by clock and reset, using pointers, full and empty signals, and a depth-eight memory, plus a test bench.
- FIFO 04 – Synchronous FIFO 03: Testbench24:06
Design and verify a synchronous fifo testbench by creating a test bench, defining timescale and clock, driving write and read operations, and validating the empty signal through simulation.
- FIFO 05 – Synchronous FIFO 04: One Extra Bit15:51
Explore a one-extra-bit technique for synchronous FIFO on Intel (Altera) FPGA using Verilog. Modify read/write pointers and full/empty logic, verify with a test bench and simplified code.
- FIFO 06 – Asynchronous FIFO: FIFO IP28:21
- Sequence Detector 01 -- Introduction2:43
Explore a sequence detector for FPGA, identifying a bit sequence in a data stream using reduced and state-machine solutions, with applications in radar and communications.
- Sequence Detector 02 -- Register Solution 015:25
- Sequence Detector 03 -- Register Solution 0217:02
Explore a reduced Verilog solution for a sequence detector on Intel (Altera) FPGA, implementing a clocked shift register, comparison logic, and a test bench with simulation to verify detection.
- Sequence Detector 04 -- State Machine Solution 019:49
- Sequence Detector 05 -- State Machine Solution 0213:46
Learn to code and simulate a sequence detector using a standard state machine in Verilog for an Intel (Altera) FPGA, detailing state definitions, next-state logic, and a test bench setup.
- Sequence Detector 06 -- State Machine Solution 038:38
Optimize a sequence detector by refining the state machine with next-state logic and removing redundant states to synchronize output with the final input bit, based on the status transition table.
- Traffic Lights Controller 01-- System Target4:47
- Traffic Lights Controller 02-- Coding & Simulation25:36
- FPGA Division 01: Solution 0119:39
Design and simulate a division module in Verilog for an Intel (Altera) FPGA, with a test bench, and evaluate FPGA resource usage in Quartus to compare solutions.
- FPGA Division 02: Solution 02 -- Analysis9:08
- FPGA Division 03: Solution 02 -- Coding17:33
Demonstrates the coding of an fpga division module in Verilog for an Altera fpga, detailing an interface, signals, a three-block state machine, and calculation and reset tasks with bit-width extension.
- FPGA Division 04: Solution 02 -- Simulation10:02
Create and simulate a division test bench in verilog for an Intel fpga, configuring clock, reset, and enable, compiling, running the simulation, and verifying outputs via waveforms.
- FPGA Division 05: Solution 02 -- Quartus Project7:05
- FPGA Division 06: Solution 03 -- Analysis5:58
Analyze the solution three FPGA division by comparing A and B, subtracting B from A, and incrementing C, implemented via a status machine with ok, calculation, and tenth states.
- FPGA Division 07: Solution 03 -- Coding10:44
Implement Verilog coding for FPGA division 07, building a three-state status machine with reset, calculation, and done tasks, and simulate to verify results.
- FPGA Division 08: Solution 03 -- Simulation11:58
- FPGA Division 09: Solution 03 -- Quartus Project7:31
- FPGA Divisoin 10: Solution 04 -- Analysis5:11
analyze a FPGA division by three solution using shifts and binary decomposition to convert numbers into a shift-friendly format, enabling left and right shifts to perform division and multiplication efficiently.
- FPGA Division 11: Solution 04 -- Coding8:59
Learn verilog coding for intel altera fpga division 11 solution 04, using a case-based flow controller with clock, reset, and enable, implementing left/right shifts and add-accumulate steps, plus simulation.
- FPGA Division 12: Solution 04 -- Simulation10:29
Master FPGA division health simulation by building a test bench with clock generation, reset and enable sequencing, and waveform verification to validate division logic.
- FPGA Division 13: Solution 04 -- Quartus Project6:03
The lecture explains how to create a Quartus project for an FPGA division solution and compare FPGA resource usage across different solutions.
- FPGA Division 14: Solution 05 -- LPM divide IP 0124:41
- FPGA Division 15: Solution 05 -- LPM divide IP 0212:41
Learn to configure the LPM divide IP 02 for FPGA division on an Intel (Altera) FPGA, build a test bench in ModelSim, and verify input–output behavior without delay.
- FPGA Mean (Average) Filter 01 -- Introduction5:03
- FPGA Mean (Average) Filter 02 -- Coding11:32
Demonstrates coding a Verilog mean filter for Intel Altera FPGA, including sum, min, max, and mean calculations with 10 data samples, clocked by always blocks and a test bench.
- FPGA Mean (Average) Filter 03 -- Simulation12:12
- FPGA Median Filter 01 -- Introduction7:17
Explore FPGA-based median filtering: collect nine data samples, sort to extract min, median, and max, and output the median for noise reduction in digital signal and image processing.
- FPGA Median Filter 02 -- Sort Module Coding9:24
Develop a Verilog sort module for an FPGA median filter by coding a three-data sorter with max, median, and min outputs, using always blocks and reset logic.
- FPGA Median Filter 03 -- Sort Module Simulation11:03
Test a sort module for a Verilog median filter on an Intel FPGA using a test bench, verifying max, min, and median outputs in simulation.
- FPGA Median Filter 04 -- Median Module Coding19:10
- FPGA Median Filter 05 -- Median Module Simulation12:07
- FPGA Gaussian Filter 01 -- Introduction9:15
Learn how to implement a gaussian filter on an FPGA using Verilog, performing convolution with a gaussian kernel, processing input data through three interfaces, and producing real-time filtered results.
- FPGA Gaussian Filter 02 -- Coding13:05
Explore Verilog coding for an FPGA gaussian filter, including module interface, data shifting, three-line convolution, reduction and sum, division by sixteen, and flow-controlled output with a six-clock ready signal.
- FPGA Gaussian Filter 03 -- Simulation11:25
Develop a verilog test bench for the intel altera fpga Kostia field, defining timescale, generating a clock, applying reset and enable, and feeding sequential data for ModelSim simulation.
- FPGA Drive Uart 01 -- System Target4:12
Develop a usb-to-uart driven fpga interface on an Intel Altera fpga, wiring a uart cable, using open source software to send data to the fpga and receive results back.
- FPGA Drive Uart 02 -- System Analysis8:43
Analyze the uart interface for driving the fpga, noting 3.3 v supply and a four-pin connect interface. Outline system blocks with uart tx/rx, clocks, and reset signaling for data transfer.
- FPGA Drive Uart 03 -- Uart Protocol7:47
This lecture explains the uart protocol for fpga, detailing the data frame, start/stop bits, bit order, and reliance on an internal clock with matched baud rate for tx and rx.
- FPGA Drive Uart 04 -- Edge Detection7:12
Explore edge-detection techniques for an FPGA UART driver, using state equations to detect single bit transitions, reduce noise, and improve signal stability with multiple registers.
- FPGA Drive Uart 05 -- Uart RX State Machine7:36
- FPGA Drive Uart 06 -- Uart RX Coding9:25
Explore UART RX coding in Verilog for Intel (Altera) FPGA, illustrating a UART receiver module with clock, reset, and input signals, an edge-detection scheme, and a one-big-timer baud generator.
- FPGA Drive Uart 07 -- Uart RX Simulation16:09
- FPGA Drive Uart 08 -- Uart TX State Machine4:37
Explore the uart tx state machine in Verilog for Intel FPGA, detailing the idle, start bit, eight data bits, and stop bit sequence and timing within the protocol.
- FPGA Drive Uart 09 -- Uart TX Coding7:53
demonstrates uart tx coding for an fpga driver using a five-state controller, a one-bit timer (0–9) with clock enable, and sequentially transmitting a byte on the tx line.
- FPGA Drive Uart 10 -- Uart TX Simulation13:05
Explore uart tx simulation for Intel Altera devices, using a test bench, clock and reset sequencing to validate data enable and output signals.
- FPGA Drive Uart 11 -- Top Module Coding and Simulation22:33
- FPGA Drive Uart 12 -- Run On Board10:27
Configure and test a UART drive on an Intel FPGA board by wiring ground, building a Quartus project, and programming via USB-Blaster to validate data exchange.
- Introduction & System Block12:08
- Driver IC Working Flow27:14
Drive a seven-segment display with an FPGA using Verilog, following the driver IC workflow with shift clock and storage clock controlling serial data into a shift register.
- Seg7_Driver() Module State Machine9:21
- Seg7_Driver() Module Coding28:50
Develop Verilog seg7 driver module for Intel fpga that drives a seven-segment display (0–9, a–f) via a state-machine with clock, reset, control signals, and shift and storage clocks.
- Seg7_Driver() Module Simulation19:10
Simulate the seg7_driver() module for a seven-segment display on an Intel (Altera) FPGA, using a test bench, clock timing, reset handling, and waveform verification to validate the segment outputs.
- Seg7_Ctrl() Module Analysis10:09
- Seg7_Ctrl() Module Coding12:29
- Seg7_Ctrl() Module Simulation15:26
- Seg7_Data() Module Analysis6:16
- Seg7_Data() Module Coding12:28
- Seg7_Data() Module Simulation14:47
Create and simulate the Seg7_Data() module by building a test bench, defining time scale, clock and reset, and input vectors, then run the project simulation to verify seven segment data.
- Seg7_Top() Module Coding & Simulation32:36
Code and simulate the seg7 top module in Verilog, wiring the control, driver, and datapath, using a one microsecond timer and test benches to debug state transitions and display timing.
- Run On Board12:06
- System Target10:11
Explore a system target for a Verilog-driven I2C EEPROM driver on an Intel Altera FPGA, covering datasheet details, I2C timing, page write and sequential read sequences, with write-read verification.
- System Analysis5:03
Explore a fpga-based system analysis of i2c communication with an eeprom, detailing clock and reset inputs, i2c master signals, and read/write control for data exchange.
- IIC Byte Write Protocol10:02
Explore the I2C byte write protocol for EEPROMs, detailing start/stop conditions, seven-bit device addresses, memory address and data bytes, and acknowledgments.
- IIC Byte Write State Machine6:26
Implement a Verilog I2C byte write state machine for Intel (Altera) FPGA. Trace I2C protocol states from idle through start, address, data, ack, and stop.
- IIC Clock Coding11:30
Generate an i2c clock for an FPGA driver by dividing a 50 mhz input to 100 khz, using a counter and an always block to create low and high phases.
- IIC Clock Simulation11:02
Create a verilog i2c clock test bench for an fpga, define timescale and clock period, generate a 100 khz i2c clock, and verify with waveform analysis.
- IIC Byte Write Coding 0122:24
Learn verilog coding for I2C byte write on an Intel FPGA. Build an I2C master with a state machine that manages read/write signals, data, address, and acknowledge handling.
- IIC Byte Write Coding 0225:55
Learn to implement an I2C byte write in Verilog using multiple always blocks, with shift-out data, start/stop conditions, acks, and read/write sequences at a 100 kHz I2C clock.
- IIC Byte Write Simulation 0116:04
Create a Verilog test bench for I2C byte write on an Intel FPGA, detailing timescale, clock, reset, enable, and write/read sequences, and verify device addresses and acknowledge signaling.
- IIC Byte Write Simulation 0211:26
- IIC Byte Read Protocol8:47
- IIC Byte Read State Machine6:09
Explore the I2C byte read state machine in Verilog for Intel FPGA, detailing read and write protocols, acknowledge handling, restarts, stops, and the shared read/write path.
- IIC Byte Read Coding20:21
Implement i2c byte read coding with a unified i2c driver and a status-driven state machine, handling restart, stop, acknowledge, and shift out/in sequences for eeprom date reads.
- IIC Byte Read Simulation17:12
Perform I2C byte read simulation for an Intel (Altera) fpga driver by modifying the test bench to exercise read sequences, acknowledgments, and data feedback through verilog case language.
- IIC User Module State Machine5:08
Explain the I2C user module state machine for an fpga driver, detailing idle, write, delay, and read states, and a delay to finish the EEPROM write cycle.
- IIC User Module Coding16:29
Code an I2C user module for an FPGA using a state machine and tasks. Implement read and write operations, delay timing, and interface signals at 50 megahertz.
- IIC User Module Simulation23:10
Explore I2C user module simulation for an FPGA driver, using Verilog test benches to verify read and write operations, clocking, and waveform analysis.
- IIC Top Module Coding5:42
- Run On Board7:07
Create and configure an I2C–based top‑level design on an Intel (Altera) cyclone FPGA, set clock and reset pins, compile and program the device, then verify on‑board operation with LED indicators.
- FPGA Drive TTP223 One Touch Sensor6:25
Learn to interface a ttp223 touch sensor with an Intel (Altera) FPGA, wire input and output signals, supply 3.3 v, and drive an LCD or indicator from touch status.
- FPGA Drive Vibration Sensor9:12
Demonstrates an FPGA PWM driver for a vibration sensor using Verilog on Intel (Altera) FPGA, generating PWM with an 8-bit counter and adjustable duty cycles via a key.
- FPGA Drive Light Sensor5:50
- FPGA Drive RGB Breathing Light6:24
Learn to implement a Verilog rgb breathing light driver on an Intel (Altera) FPGA, using a period counter and a direction flag to modulate brightness with high and low levels.
Requirements
- FPGA basic knowledge
Description
This series of lessons base on Intel (Altera) FPGA. It will include the content as follows:
(1) Verilog basic knowledge and coding skill;
(2) FPGA basic knowledge and concept;
(3) How to use Intel FPGA Quartus software and USB Blaster for coding and debugging.
(4) How to use modelsim for simulation.
(5) It will discuss some verilog examples in detail, such as, clock divider, fifo, ram, rom, 7 segment dispaly, uart, sequence detector, keyboard etc.
Who this course is for:
- Freshman for intel FPGA
- Beginner of verilog design