Verilog on Intel (Altera) FPGA

Name: Verilog on Intel (Altera) FPGA
Rating: 4.2 (67 reviews)

Basic Lessons

Created byHUI HU

Last updated 9/2021

English

What you'll learn

Verilog basic knowledge
Verilog coding skill
How to use intel FPGA tools, such as Quartus, Modelsim, USB Blaster etc.
Drive all kinds of sensors

Course content

6 sections • 96 lectures • 21h 1m total length

Compile Environment Setup---Quartus & ModelSim10:07
For anyone who needs the compile software, you can download it directly from the following linker:
(1) cyclone-19.1.0.670.qdz ---
https://drive.google.com/file/d/1wPpb99pMdV6mKIYU8QijaW0ztcmBj_YA/view?usp=sharing

(2) ModelSimSetup-19.1.0.670-windows.exe ---
https://drive.google.com/file/d/1iTCKc_J5vsBFA7wHX6euhM-SLHdEYXb3/view?usp=sharing

(3) QuartusLiteSetup-19.1.0.670-windows.exe ---
https://drive.google.com/file/d/15xcpywAm4xer4DumYOJ-mjJLupHIZZVJ/view?usp=sharing
Simplest LED “Hello, World!”15:59
Simplest Testbench16:48
ModelSim16:32
USB Blaster26:43
Clock Divider 01 – Analysis & Coding22:12
Clock Divider 02 – Simulation34:03
Clock Divider 03 – PLL IP27:47
FIFO 01 – Introduction11:16
FIFO 02 – Synchronous FIFO 01: Analysis8:14
FIFO 03 – Synchronous FIFO 02: Coding26:06
FIFO 04 – Synchronous FIFO 03: Testbench24:06
FIFO 05 – Synchronous FIFO 04: One Extra Bit15:51
FIFO 06 – Asynchronous FIFO: FIFO IP28:21
Sequence Detector 01 -- Introduction2:43
Sequence Detector 02 -- Register Solution 015:25
Sequence Detector 03 -- Register Solution 0217:02
Sequence Detector 04 -- State Machine Solution 019:49
Sequence Detector 05 -- State Machine Solution 0213:46
Sequence Detector 06 -- State Machine Solution 038:38
Traffic Lights Controller 01-- System Target4:47
Traffic Lights Controller 02-- Coding & Simulation25:36

FPGA Division 01: Solution 0119:39
FPGA Division 02: Solution 02 -- Analysis9:08
FPGA Division 03: Solution 02 -- Coding17:33
FPGA Division 04: Solution 02 -- Simulation10:02
FPGA Division 05: Solution 02 -- Quartus Project7:05
FPGA Division 06: Solution 03 -- Analysis5:58
FPGA Division 07: Solution 03 -- Coding10:44
FPGA Division 08: Solution 03 -- Simulation11:58
FPGA Division 09: Solution 03 -- Quartus Project7:31
FPGA Divisoin 10: Solution 04 -- Analysis5:11
FPGA Division 11: Solution 04 -- Coding8:59
FPGA Division 12: Solution 04 -- Simulation10:29
FPGA Division 13: Solution 04 -- Quartus Project6:03
FPGA Division 14: Solution 05 -- LPM divide IP 0124:41
FPGA Division 15: Solution 05 -- LPM divide IP 0212:41
FPGA Mean (Average) Filter 01 -- Introduction5:03
FPGA Mean (Average) Filter 02 -- Coding11:32
FPGA Mean (Average) Filter 03 -- Simulation12:12
FPGA Median Filter 01 -- Introduction7:17
FPGA Median Filter 02 -- Sort Module Coding9:24
FPGA Median Filter 03 -- Sort Module Simulation11:03
FPGA Median Filter 04 -- Median Module Coding19:10
FPGA Median Filter 05 -- Median Module Simulation12:07
FPGA Gaussian Filter 01 -- Introduction9:15
FPGA Gaussian Filter 02 -- Coding13:05
FPGA Gaussian Filter 03 -- Simulation11:25

FPGA Drive Uart 01 -- System Target4:12
FPGA Drive Uart 02 -- System Analysis8:43
FPGA Drive Uart 03 -- Uart Protocol7:47
FPGA Drive Uart 04 -- Edge Detection7:12
FPGA Drive Uart 05 -- Uart RX State Machine7:36
FPGA Drive Uart 06 -- Uart RX Coding9:25
FPGA Drive Uart 07 -- Uart RX Simulation16:09
FPGA Drive Uart 08 -- Uart TX State Machine4:37
FPGA Drive Uart 09 -- Uart TX Coding7:53
FPGA Drive Uart 10 -- Uart TX Simulation13:05
FPGA Drive Uart 11 -- Top Module Coding and Simulation22:33
FPGA Drive Uart 12 -- Run On Board10:27

Introduction & System Block12:08
Driver IC Working Flow27:14
Seg7_Driver() Module State Machine9:21
Seg7_Driver() Module Coding28:50
Seg7_Driver() Module Simulation19:10
Seg7_Ctrl() Module Analysis10:09
Seg7_Ctrl() Module Coding12:29
Seg7_Ctrl() Module Simulation15:26
Seg7_Data() Module Analysis6:16
Seg7_Data() Module Coding12:28
Seg7_Data() Module Simulation14:47
Seg7_Top() Module Coding & Simulation32:36
Run On Board12:06

System Target10:11
System Analysis5:03
IIC Byte Write Protocol10:02
IIC Byte Write State Machine6:26
IIC Clock Coding11:30
IIC Clock Simulation11:02
IIC Byte Write Coding 0122:24
IIC Byte Write Coding 0225:55
IIC Byte Write Simulation 0116:04
IIC Byte Write Simulation 0211:26
IIC Byte Read Protocol8:47
IIC Byte Read State Machine6:09
IIC Byte Read Coding20:21
IIC Byte Read Simulation17:12
IIC User Module State Machine5:08
IIC User Module Coding16:29
IIC User Module Simulation23:10
IIC Top Module Coding5:42
Run On Board7:07

Requirements

FPGA basic knowledge

Description

This series of lessons base on Intel (Altera) FPGA. It will include the content as follows:

(1) Verilog basic knowledge and coding skill;

(2) FPGA basic knowledge and concept;

(3) How to use Intel FPGA Quartus software and USB Blaster for coding and debugging.

(4) How to use modelsim for simulation.

(5) It will discuss some verilog examples in detail, such as, clock divider, fifo, ram, rom, 7 segment dispaly, uart, sequence detector, keyboard etc.

Who this course is for:

Freshman for intel FPGA
Beginner of verilog design

Verilog on Intel (Altera) FPGA

What you'll learn

Explore related topics

Course content

Basic22 lectures • 6hr 12min

FPGA Division26 lectures • 4hr 49min

FPGA Drive Uart12 lectures • 2hr

FPGA Drive 7 Segment Display13 lectures • 3hr 33min

FPGA Drive IIC EEPROM19 lectures • 4hr

Sensors4 lectures • 28min

Requirements

Description

Who this course is for: