Verilog HDL: VLSI Hardware Design Comprehensive Masterclass
4.2 (29 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
102 students enrolled

Verilog HDL: VLSI Hardware Design Comprehensive Masterclass

From an expert with 15+ years experience. Core Design principles for VLSI, Soc, Processor and FPGA. VHDL alternative.
4.2 (29 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
102 students enrolled
Last updated 7/2020
English
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Current price: $139.99 Original price: $199.99 Discount: 30% off
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This course includes
  • 12 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Assignments
  • Certificate of Completion
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What you'll learn
  • Unlimited instructor support !
  • Application Specific Integrated Circuit (ASIC) design flow and its related fundamentals
  • Learn more than enough to start designing real life circuits using HDL
  • Have a clear understanding of how to and how not to write a piece of HDL code
  • The close relationship between hardware and code
  • From basics to key principles for design engineers
  • A detailed discussion on every bit of code and hardware
Requirements
  • Mandatory: A passion to learn and practice regularly and systematically
  • Basics of Digital Logic Design
  • Fundamentals of VLSI
  • Optional: Any coding experience shall help although not necessary
  • Computer architecture
Description

A job oriented exhaustive course on logic design for hardware using the Verilog Hardware Description Language.

Unique, tested and proven structured style and approach followed.

Thoughtful blend of theory and practice for your learning.

Unlimited support with the instructor.

Understand all the intricate details in thinking and understanding hardware design.

Principles are reinforced with multiple examples.

Good coding guidelines and bad examples to avoid.

After completing the course, you can confidently write synthesizable code for complex hardware design.

Thorough discussion of every hardware component design.

Detailed explanation of the relationship between code and digital hardware units.

Freely download 100+ code examples and test benches used in the course.

Access to all the materials and the future upgrades.

Loads to quizzes and assignments to check your understanding.

Work through the lessons at your own pace.

Who this course is for:
  • A beginner or an intermediate - eager to grasp and understand Hardware Design concepts with HDL
  • Anyone aspiring to build a career in VLSI Circuit Design
  • If you are in the industry and would like to sharpen your skills and clarify your understanding
Course content
Expand all 134 lectures 11:56:46
+ Introduction
29 lectures 01:52:25
Review of VLSI concepts
02:12
What is VLSI?
01:55
Review of terms
02:36
Minimum feature size
00:48
VLSI Design Styles - Full Custom
07:37
VLSI Design Styles - Semi Custom
03:17
VLSI Design Styles - FPGA
04:54
VLSI Design Styles - Gate Array
02:08
VLSI Design Styles - Comparison
04:22
Full custom vs Semi custom
03:11
ASIC vs FPGA
04:05
ASIC Design Flow - Part 2
05:39
ASIC Design Flow - Design Specs
02:44
ASIC Design Flow - Architecturing
03:27
ASIC Design Flow - RTL coding
01:23
ASIC Design Flow - Verification
03:47
ASIC Design Flow - Synthesis
04:42
ASIC Design Flow - Design for Testability
08:03
ASIC Design Flow - Timing Analysis
02:26
ASIC Design Flow - Floorplanning, Placement & Routing
03:44
ASIC Design Flow - Formal Verification
01:14
ASIC Design Flow - Power Estimation
01:22
ASIC Design Flow - Fabrication
00:22
ASIC Design Flow - Packaging
01:16
+ Verilog Basics
10 lectures 01:03:02
Verilog Design Styles
02:51
My First Dataflow Style Design
07:47
My First Behavioral Style Design
06:55
My First Structural Style Design
06:05
1-bit Full Adder (Sturctural-1)
08:08
1-bit Full Adder (Sturctural-2)
05:53
1-bit Full Adder (Sturctural-3)
05:56
1-bit Full Adder (Dataflow)
02:33
1-bit Full Adder (Behavioral)
02:39
My first Test Bench
14:15
+ Designing Combinational Logic
37 lectures 04:19:35
4 Valued Logic
16:42
Data Types
04:33
Number Representation
13:22
Bit and Bus
04:42
Naming Conventions
03:42
Operators - Bitwise
17:19
Operators - Arithmetic
16:01
Operators - Logical
16:51
Operators - Relational
07:24
Operators - Reduction
10:56
Operators - Shift
08:37
Operators - Concatenation
04:15
Operators - Repetition
02:08
Operators - Conditional
04:03
Output Resolution Table
10:40
4-bit Full Adder (Dataflow)
01:56
4-bit Full Adder (Behavioral)
01:26
4-bit Full Adder Test Bench
08:37
2:1 Multiplexer (Dataflow)
02:23
2:1 Multiplexer (Behavioral)
04:07
4:1 Multiplexer (Dataflow1)
02:21
4:1 Multiplexer (Dataflow2)
06:47
4:1 Multiplexer (Dataflow3)
03:15
4:1 Multiplexer (Behavioral)
03:44
2 X 4 Decoder (Dataflow)
05:31
2 X 4 Decoder (Behavioral)
05:22
3 X 8 Decoder (Dataflow)
01:22
4 X 2 Encoder (Dataflow)
06:50
4 X 2 Encoder (Behavioral)
08:33
4 X 2 Priority Encoder (Behavioral)
05:45
4 X 2 Priority Encoder (Dataflow)
04:22
4-bit Comparator (Dataflow 1)
06:44
4-bit Comparator (Dataflow 2)
03:41
4-bit Comparator (Behavioral)
00:58
8-bit Barrel Shifter (Combinational Left & Right)
20:21
Designing Arithmetic & Logic Unit (ALU)
08:02
+ Designing Sequential Logic
29 lectures 02:35:10
Clock, D-Latch and a D-Flip Flop
09:07
D-Flip Flop vs D-Latch
07:48
D-Latch (Dataflow)
02:11
D-Latch (Behavioral)
01:49
D-Latch with Asynchronous Reset (Behavioral)
01:31
D-Flip Flop (Basic)
05:31
Postitive Edge Triggered D-Flip Flop with Asynchronous Active High Reset
05:10
Negative Edge Triggered D-Flip Flop with Asynchronous Active High Reset
03:21
Postitive Edge Triggered D-Flip Flop with Asynchronous Active Low Reset
01:33
Postitive Edge Triggered D-Flip Flop with Asynchronous Active High Set
02:55
Synchronous D-Flip Flop with Active Low Reset
00:48
Synchronous D-Flip Flop with Reset and Set
01:37
Synchronous and Asynchronous Reset Design
10:48
8-bit Twin Register Set
03:27
Designing a 5-bit Left to Right Shift Register
11:06
Designing a 5-bit Universal Shift Register
06:01
Designing a basic counter
03:58
Writing a Test Bench for a Counter
02:55
Designing an Up Counter with Load Option
02:53
Designing an Up or Down Counter
02:35
Designing a Modulus Counter
03:56
Designing a Range Up Counter
03:56
Designing a Range Up or Down Counter with Load Option
08:49
Designing a Clock Frequency Divider (Divide by 2)
04:09
Designing a Clock Frequency Divider (Divide by 4)
03:54
Designing a Clock Frequency Divider (Divide by 3)
08:41
Designing a Single Clock First In First Out (FIFO)
24:40
Designing a Dual Clock First In First Out (FIFO)
07:07
+ Designing Memories
9 lectures 42:42
Memory Array Options and Definitions
13:09
Single Port Ram - v1
07:50
Single Port Ram - v2
02:28
Single Port Ram - v3
02:56
Single Port Ram - v4
01:29
Dual Port Ram - v1
03:36
Dual Port Ram - v2
01:36
True Dual Port Ram - v1
06:05
True Dual Port Ram - v2
03:33
+ Designing Finite State Machines
20 lectures 01:23:52
Mealy vs Moore Machine
06:20
Mealy - 101 Non-Overlapping Sequence Detector
04:14
Mealy - 011 Non-Overlapping Sequence Detector
01:59
Mealy - 000 Non-Overlapping Sequence Detector
01:54
Mealy - 0101 Non-Overlapping Sequence Detector
02:26
Mealy - 11011 Non-Overlapping Sequence Detector
02:37
Mealy - 101 Overlapping Sequence Detector
02:22
Mealy - 011 Overlapping Sequence Detector
01:31
Mealy - 000 Overlapping Sequence Detector
01:45
Mealy - 0101 Overlapping Sequence Detector
02:25
Mealy - 11011 Overlapping Sequence Detector
02:39
Designing a Mealy Machine - Sequence Detector
15:45
Moore - 101 Non-Overlapping Sequence Detector
04:20
Moore - 010 Non-Overlapping Sequence Detector
02:26
Moore - 0101 Non-Overlapping Sequence Detector
02:59
Moore - 101 Overlapping Sequence Detector
02:36
Moore - 010 Overlapping Sequence Detector
02:09
Moore - 0101 Overlapping Sequence Detector
02:30
Designing a Moore Machine - Sequence Detector
08:42
Designing a Machine to Pick a Series of Coloured Balls and a Vending Machine
12:13