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Verilog HDL: VLSI Hardware Design Comprehensive Masterclass

From an expert with 15+ years experience. Core Design principles for VLSI, Soc, Processor and FPGA. VHDL alternative.

Bestseller

Created byShepherd Tutorials

Last updated 11/2022

English

What you'll learn

Unlimited instructor support !
Application Specific Integrated Circuit (ASIC) design flow and its related fundamentals
Learn more than enough to start designing real life circuits using HDL
Have a clear understanding of how to and how not to write a piece of HDL code
The close relationship between hardware and code
From basics to key principles for design engineers
A detailed discussion on every bit of code and hardware

Course content

6 sections • 135 lectures • 12h 41m total length

Introduction0:35
Get the basics right to lay a strong foundation
Course coverage5:53
Review of VLSI concepts2:12
Quick CMOS basics (added as per request)39:45
What is VLSI?1:55
Review of terms2:36
Minimum feature size0:48
Why Integration?3:55
Broad areas in VLSI11:19
VLSI Design Styles - Full Custom7:37
VLSI Design Styles - Semi Custom3:17
VLSI Design Styles - FPGA4:54
VLSI Design Styles - Gate Array2:08
VLSI Design Styles - Comparison4:22
Full custom vs Semi custom3:11
ASIC vs FPGA4:05
ASIC Design Flow - Part 113:29
ASIC Design Flow - Part 25:39
ASIC Design Flow - Design Specs2:44
ASIC Design Flow - Architecturing3:27
ASIC Design Flow - RTL coding1:23
ASIC Design Flow - Verification3:48
ASIC Design Flow - Synthesis4:42
ASIC Design Flow - Design for Testability8:03
ASIC Design Flow - Timing Analysis2:26
ASIC Design Flow - Floorplanning, Placement & Routing8:08
ASIC Design Flow - Formal Verification1:14
ASIC Design Flow - Power Estimation1:22
ASIC Design Flow - Fabrication0:22
ASIC Design Flow - Packaging1:16

4 Valued Logic16:42
Data Types4:33
Number Representation13:22
Bit and Bus4:42
Naming Conventions3:42
Operators - Bitwise17:19
Operators - Arithmetic16:01
Operators - Logical16:51
Operators - Relational7:24
Operators - Reduction10:56
Operators - Shift8:37
Operators - Concatenation4:15
Operators - Repetition2:08
Operators - Conditional4:03
Output Resolution Table10:40
4-bit Full Adder (Structural)6:13
4-bit Full Adder (Dataflow)1:56
4-bit Full Adder (Behavioral)1:26
4-bit Full Adder Test Bench8:37
2:1 Multiplexer (Dataflow)2:23
2:1 Multiplexer (Behavioral)4:07
4:1 Multiplexer (Dataflow1)2:22
4:1 Multiplexer (Dataflow2)6:47
4:1 Multiplexer (Dataflow3)3:15
4:1 Multiplexer (Behavioral)3:44
2 X 4 Decoder (Dataflow)5:31
2 X 4 Decoder (Behavioral)5:22
3 X 8 Decoder (Dataflow)1:22
4 X 2 Encoder (Dataflow)6:50
4 X 2 Encoder (Behavioral)8:33
4 X 2 Priority Encoder (Behavioral)5:45
4 X 2 Priority Encoder (Dataflow)4:22
4-bit Comparator (Dataflow 1)6:44
4-bit Comparator (Dataflow 2)3:41
4-bit Comparator (Behavioral)0:58
8-bit Barrel Shifter (Combinational Left & Right)20:22
Designing Arithmetic & Logic Unit (ALU)8:02

Clock, D-Latch and a D-Flip Flop9:07
D-Flip Flop vs D-Latch7:48
D-Latch (Dataflow)2:11
D-Latch (Behavioral)1:49
D-Latch with Asynchronous Reset (Behavioral)1:31
D-Flip Flop (Basic)5:31
Postitive Edge Triggered D-Flip Flop with Asynchronous Active High Reset5:10
Negative Edge Triggered D-Flip Flop with Asynchronous Active High Reset3:21
Postitive Edge Triggered D-Flip Flop with Asynchronous Active Low Reset1:33
Postitive Edge Triggered D-Flip Flop with Asynchronous Active High Set2:55
Synchronous D-Flip Flop with Active High Reset2:54
Synchronous D-Flip Flop with Active Low Reset0:48
Synchronous D-Flip Flop with Reset and Set1:37
Synchronous and Asynchronous Reset Design10:48
8-bit Twin Register Set3:28
Designing a 5-bit Left to Right Shift Register11:07
Designing a 5-bit Universal Shift Register6:01
Designing a basic counter3:58
Writing a Test Bench for a Counter2:55
Designing an Up Counter with Load Option2:53
Designing an Up or Down Counter2:35
Designing a Modulus Counter3:56
Designing a Range Up Counter3:57
Designing a Range Up or Down Counter with Load Option8:49
Designing a Clock Frequency Divider (Divide by 2)4:09
Designing a Clock Frequency Divider (Divide by 4)3:54
Designing a Clock Frequency Divider (Divide by 3)8:41
Designing a Single Clock First In First Out (FIFO)24:40
Designing a Dual Clock First In First Out (FIFO)7:07

Mealy vs Moore Machine6:20
Mealy - 101 Non-Overlapping Sequence Detector4:14
Mealy - 011 Non-Overlapping Sequence Detector1:59
Mealy - 000 Non-Overlapping Sequence Detector1:54
Mealy - 0101 Non-Overlapping Sequence Detector2:26
Mealy - 11011 Non-Overlapping Sequence Detector2:37
Mealy - 101 Overlapping Sequence Detector2:22
Mealy - 011 Overlapping Sequence Detector1:31
Mealy - 000 Overlapping Sequence Detector1:45
Mealy - 0101 Overlapping Sequence Detector2:25
Mealy - 11011 Overlapping Sequence Detector2:39
Designing a Mealy Machine - Sequence Detector15:45
Moore - 101 Non-Overlapping Sequence Detector4:20
Moore - 010 Non-Overlapping Sequence Detector2:26
Moore - 0101 Non-Overlapping Sequence Detector2:59
Moore - 101 Overlapping Sequence Detector2:36
Moore - 010 Overlapping Sequence Detector2:09
Moore - 0101 Overlapping Sequence Detector2:30
Designing a Moore Machine - Sequence Detector8:42
Designing a Machine to Pick a Series of Coloured Balls and a Vending Machine12:13

Requirements

Mandatory: A passion to learn and practice regularly and systematically
Basics of Digital Logic Design
Fundamentals of VLSI
Optional: Any coding experience shall help although not necessary
Computer architecture

Description

A job oriented exhaustive course on logic design for hardware using the Verilog Hardware Description Language.

Unique, tested and proven structured style and approach followed.

Thoughtful blend of theory and practice for your learning.

Unlimited support with the instructor.

Understand all the intricate details in thinking and understanding hardware design.

Principles are reinforced with multiple examples.

Good coding guidelines and bad examples to avoid.

After completing the course, you can confidently write synthesizable code for complex hardware design.

Thorough discussion of every hardware component design.

Detailed explanation of the relationship between code and digital hardware units.

Freely download 100+ code examples and test benches used in the course.

Access to all the materials and the future upgrades.

Loads to quizzes and assignments to check your understanding.

Work through the lessons at your own pace.

Who this course is for:

A beginner or an intermediate - eager to grasp and understand Hardware Design concepts with HDL
Anyone aspiring to build a career in VLSI Circuit Design
If you are in the industry and would like to sharpen your skills and clarify your understanding