Verilog Programming with Xilinx ISE Tool & FPGA

Name: Verilog Programming with Xilinx ISE Tool & FPGA
Rating: 3.4 (91 reviews)

In 4.5 hours you will: Create VHDL Design, Write Simulation Testbenches,Implement Design with Xilinx ISE Tool & FPGA.

Created byDigitronix Nepal

Last updated 9/2022

English

What you'll learn

Familiar with Verilog HDL Syntax and Semantics.
Use fundamental Verilog constructs to create simple designs.
Creating Synthesizable designs in Verilog HDL
To Create Simulation testbench on Verilog and generating waveform's.
Use of Conditional Statements as If, Case & Loops with Always block for designing different combinational and sequential components.
Use Xilinx ISE Design Suit (license of ISE is Free) for FPGA/ASIC based design in Verilog.
Design with structural design methodology on Verilog.
Create a PROM File with ISE and Program PROM of FPGA

Course content

11 sections • 22 lectures • 5h 33m total length

How to download and install Xilinx ISE Design Suit & get free License4:56
This Session will explained on "How can you download the ISE Design Suit from Xilinx, Install it and get one year full webpack license". You have to install the ISE for doing the lab session with this course, so go through the lecture and ready for the lab session.
Introduction and Basic Design with Verilog HDL26:24
Verilog is an Hardware Description Language used heavily for hardware design, synthesis, timing analysis , test analysis, simulation and implementation. The Verilog HDL is an IEEE standard - number 1364. The first version of the IEEE standard for Verilog was published in 1995. A revised version was published in 2001; this is the version used by most Verilog users.

The Verilog HDL is now maintained by a non profit making organization, Accellera, which was formed from the merger of Open Verilog International (OVI) and VHDL International. OVI had the task of taking the language through the IEEE standardization procedure.

In this Lecture we have talk on Overview of Verilog, Verilog Design Flow on FPGA Design, abstraction level of verilog, Basic Example of Verilog and Data Type/Operator of Verilog in detail. After completing this session you will have brief idea of Verilog, syntax of Verilog, Data type and operators.
Multiple Choice Question
Multiple Choice Question related with Module,Input and Output declaration
Example of How to Write Verilog Program for Basic Logic Gate:AND in Xilinx ISE7:02
In this section you will do the complete design flow of Designing AND Gate on Verilog,Synthesizing it, Creating and Simulating with Testbench (Testfixture), Implementing AND Gate with Constraint and Finally Generating the Project (i.e creating Bitstream or .bit file). You will learn all the necessary steps and method of Verilog Design Flow in the fast track, so you will get confidence while doing other lab.
Operators , Data Type and Basic Syntax
Design Simulation and Implementation of NAND Gate on ISE and Spartan 3E FPGA19:39
Basic Logic Gate Design with Verilog HDL and ISE Design Suit has been shown on this lecture You will design basic logic gate (NAND) on Verilog, Synthesize the NAND Gate, write a Simulation Testbench/Testfixture for creating waveform of NAND gate and Finally we are going to implement the NAND gate with Constraint of Spartan 3E/Nexys 2 FPGA. At the end of this lecture a bitstream has been generated which we are going to use to program FPGA on another Session.
Demo-NAND Gate Implementation on Spartan 3E0:48

Simulating Verilog Code with Testfixture: Simulating Logic Gate on ISE22:36
Simulation is the process of creating a vertual environment for the real time operation. In FPGA Design simulation is the process of generating waveform of different input state and corresponding output state. The Simulation provides the result which we are going to achieved on the hardware implementation, so the simulation is mostly followed for FPGA Design. ISE Design suit has inbuilt simulator which can simulate the testbench/testfixture type of simulation source and generate timing waveform. The simulation is the mostly preferred and done design process in FPGA design while the simulation process gives the exact result then only the design engineer proceed for Hardware Implementation of functionality.
In this lecture we are going to learn about how to write simulation testbench/testfixture for simulating a basic logic gate.
Introduction to Simulation and Testbench MCQ's
DUT MCQ's

Conditional Statements in Verilog HDL (4:1 MUX Design & Simulation)25:53
Conditional Statements are those statements which gives one output or statement when one condition is true and gives another output statement when the condition is false. so it checks a boolean expression and sends the flow of program on true or false situation.

In this lecture we have presented about different conditional statements as IF Statement, case statement, how to insert those conditional statement in Always Block, what is posedge @clk statement etc.
This is the Complete Video Series of this Section 3: Conditional Statement in Verilog. All the Lectures listed below in section 4 are taught in this video so you could Learn from video and from the Lectures/Articles and Quiz listed below.
Quiz on the concept of always block
Quiz on IF statement
Quiz on Case Statement

Combinational Circuit Design in Verilog (Full Adder Design & Simulation) II35:06
Combinational Circuit are those circuit which takes some inputs and gives some combination of output. so the combinnational circuit are directly dependent on the current input. In this lecture we have discussed about different combinational circuit and we have desgin Full Adder which takes three inputs and gives sum and carry as output. We also have created a simulation testbench and generated simulation waveform for checking the functionality of Full Adder before implementation on real FPGA.

This Video is the complete Video of the Section 4: Combinaitnal Circuit Design in Verilog. All the Lectures listed below in section 4 are taught in this video so you could Learn from video and from the Lectures/Articles and Quiz listed below.
Section 4 2 Implementation on Full Adder on Spartan 3E FPGA4:53
In this lab we have implemented Full Adder designed on previous section, we have synthesized the Full adder , simulated it on previous lecture now we have placed the constraint for Full adder implementation on Spartan 3E FPGA. After the implementation the Bitstream Generation process has been done, this bit file is going to used on next session for implementing/uploading it on FPGA.
Demo: Full Adder Implementation on Spartan 3E FPGA0:49
In this lecture we can see the demonstration of Full adder on Spartan 3E/Nexys 2 or other FPGA if you target for . We have verified the functionality of Full Adder on FPGA with providing three inputs and observing the two output's.
Basic Combinaitonal Circuit concepts
Quiz on Combination of gate design
Quiz on Decoder Design in Verilog
Encoder (16:4) Design and Simulation in Verilog with ISE Design Suit13:53
In this lecture we have designed Encoder (2^n-->n) combinational circuit which encodes or converts 2^n data in to n data. Encoder can be of 16:4, 8:3, 4:2 etc. In this lecture we have design and simulate the 16:4 encoder on Verilog with ISE Design suit. From the simulation waveform we can validate/verify the functionality of encoder and its truth table.

Sequential Circuits Design in Verilog (Flip-Flop Design & Simulation)32:37
Sequential Circuit are those circuit which takes combinational inputs and also takes the past output for generating the current output. so the sequential circuit consists of memory elements for generating outputs. examples of sequential circuit are flipflop, register, counter etc. In this Lecture we are going to design a Flip-Flop circuit (D Flip-Flop) and we are going to see the simulation waveform of D FF.
Quiz on Latch Design
Quiz on Flipflop
Quiz on Register Design in Verilog
FSM Design in Verilog (State Machine: Sequence Detector Design and Simulation)14:14
Finite state machine are those logical block on Digital Design which is used to solve any problem by differentiating different condition on define number of state. So in each define number of state some input might varry which generate some output and change the current state in to another state. Examples of Finite Machine Design implemented are Traffic Light Controller, Vending Machine Design, Car Parking and alarming system etc. The FSM is highly used methodology for solving real time problems with define number of state and state diagram representation.
Quiz on FSM Design

Structural Design in Verilog (Designing of 4 bit Full Adder-F.A using 1 bit F.A)31:25
Structural Design is the concept of utilizing previously written/scripted module on the recent module so the code resuability can be achieved. The Structural Design Approach make more easy to architect the larger project in to small parts and finally assembling it in to single one. While we design with Structural Design approach the called module has to be included on the same project to.
Structural Design Basics Quiz
Structural Design : Module Integration Quiz

Section 7_1 How to Create PROM file and Upload on FPGA6:54
In this lecture we have introduce how to program PROM of Spartan 3E/Nexys 2 FPGA and There is another SPI PROM on Spartan 3E which can be programmed for bit file size more than 4 Mbit and less than 16 Mbit.
So we have attached tutorial of How to program PROM and SPI PROM on Spartan 3E/ Nexys FPGA.
We also have attached the Verilog Reference Guide for Students (Up to intermediate learners) in this Lecture which will very much helpful for learning Verilog intermediate Skills.

Requirements

Basic Idea of C Programming
Familiarity with Digital Logic Design
Hardware Design Basics
Basic Idea of Logic Simulation

Description

>>>> This is Crash Course on Verilog Programming which includes Verilog Basics to Advance Design <<<<

This Course of Verilog HDL Programming for Beginners is targeted for those enthusiasts and beginners who want to get idea of Verilog, Its programming methodology, Syntax, Operators, Always Block,Conditional Statements-Case/IF else, Writing Simulation Testbench etc. We have started this course from very basic to the designing combinational and sequential circuits (including Finite State Machine) Design.We have used Xilinx ISE Design suit in this course because of it's License is free from Xilinx (You just need to make a user account and follow: our Video Lecture on this Course "How to Get free Xilinx ISE Design suit License" ).

We have showed up you the implementation of Projects of ISE and Spartan 3E & Nexys 2 FPGA and there are some Demo of the implementation on Spartan 3E & Nexys 2FPGA. Finally we have Session on "How to Create PROM File with ISE and Program PROM of Spartan 3E & Nexys 2 FPGA".

The objective of this course is to explore verilog basics, how can project on Xilinx ISE be developed, how to synthesize the design, implement , how to analyse the RTL schematic and how to write constraint for the custom verilog project.

So you can practice this course on Xilinx ISE Design Suit or Altera Quartus Suit.

Who this course is for:

Electronics Engineering and Computer Science
Electrical Engineering
Computer Engineering
Hardware Design with FPGA enthusiasts
Digital Design with FPGA enthusiasts

Verilog Programming with Xilinx ISE Tool & FPGA

What you'll learn

Explore related topics

Course content

Section 1 Introduction and Basic Design with Verilog5 lectures • 59min

Section 2 Simulating Verilog Code with Testbench/Testfixture1 lecture • 23min

Section 3 Conditional Statement in Verilog (4:1 MUX Design and Simulation)1 lecture • 26min

Section 4 Combinational Circuit Design with Verilog (Full Adder/Encoder Design)4 lectures • 55min

Section 5 Sequential Circuit Design with Verilog (Flip-Flop and FSM Design)2 lectures • 47min

Section 6 Structural Design with Verilog (Structural Design of 4 bit Full Adder)1 lecture • 31min

8 bit ALU Design and Simulation on Verilog1 lecture • 2min

Section 7 Creating PROM File from ISE Design Suit and Uploading to FPGA1 lecture • 7min

Verilog Programming Reference Guide from Digitronix Nepal1 lecture • 22min

Summary: Verilog Programming3 lectures • 1hr 2min

Requirements

Description

Who this course is for: