Verilog HDL Fundamentals for Digital Design and Verification

Learn basic notions about Electronics Design Automation and the role of Simulation tools for the Verilog Hardware Description Language.

We will install a complete development environment from Intel FPGA. With it we will be able to simulate and synthesize our designs. All these tools are used only in Academic purposes.

Important Modelsim Installation Note

Download link: https://www.altera.com/downloads/fpga-development-tools/quartus-prime-lite-edition-design-software-version-25-1-windows

If you select Quartus Prime Lite Edition v21.1 (March 2021) you can see that it contains:

1. Quartus Prime (includes Nios II EDS)

2. Questa - Intel FPGA Edition(includes Starter Edition)

If you select Quartus Prime Lite Edition v20.1.1 (November 2020) you can see that it contains:

1. Quartus Prime (includes Nios II EDS)

2. ModelSim-Intel FPGA Edition (includes Starter Edition)

Modelsim and Questasim are products from Mentor that have the same menus, windows and appearance the sole difference being : "Questa Sim offers high-performance and advanced debugging capabilities, while ModelSim PE is the entry-level simulator for hobbyists and students. Questa Sim is used in large multi-million gate designs, and is supported on Microsoft Windows and Linux, in 32-bit and 64-bit architectures"

So you have 2 solutions and you may choose whatever you like:

1. Download version v21.1 and use Questa in the same way we use Modelsim (they will look the same for you)

2. Download version v20.1.1 and use Modelsim as the course suggests

Please contact me if you have issues installing the simulator and run the "Hello world" example. You can also contact me if you have any course related question and we'll definitely solve them.

All the best,

Ovidiu

This is your first simulation of Verilog code using a Modelsim project.

Congrats! Be proud that you've simulated your first piece of Verilog code!

Discover the 3 major groups of value objects used in digital design and verification with Verilog: Nets, Variables, and Parameters.

Write and simulate the Verilog code that calculates the sum and the product of two numbers.

Get familiar with the Verilog data types used to describe a hardware circuit.

Create a Verilog example where you perform logical operations between some variables using multiple procedures.

Learn how to represent data in a specific format using Verilog.

Play with several representation formats for data used in Verilog.

Learn how to handle multi-bit variables in Verilog.

A simple yet powerful example with vectors in Verilog.

As all programming languages Verilog has a set of powerful operators used to handle data, model behavior, and take decisions.

Verilog bit-wise operators are used to perform bit-by-bit logic operations between two inputs.

Perform several bit-wise operations between two vectors.

Verilog reduction operators are used to perform operations between the bits of the operand. The result is a 1ibt value.

A simple example where you exercise all the Verilog reduction operators.

Discover the simplicity behind Verilog logical operators.

A simple example where you will use Verilog logical operators.

In this example you will learn how and where to actually use Verilog logical operators. Using them wrong could lead to undesired behavior that is hard to debug.

Verilog also has all the simple mathematical operators that everybody knows. Check them out!

A simple exercise with all the Verilog arithmetic operators.

Shifting operations are the very core of data handling. Let's discover the logic shift and the arithmetic shift Verilog operators.

Let's shift some data using all the Verilog shift operators.

Verilog relational operators are used to compare data. The result of a comparison is 1bit and it can have the value 0 / 1 / X.

Let's compare some data using the Verilog relational operators!

Discover the case equality and logical equality Verilog operators.

Let's compare some data using the Verilog equality operators!

Discover the conditional operator. This operator takes 3 operand that's why it is also called a ternary operator.

Let's do a simple example for the conditional operator!

The concatenation operator is used to join bits from different sources for creating new buses.

In this easy example you'll learn how to use the Verilog concatenation operator.

The Verilog replication operator is used to make data patterns.

This easy example will show you how to use the Verilog replication operator.

Operators precedence is a mechanism that says what operators get to execute first in an expression. It is extremely important to know this concept as complex expressions may hide faulty behavior if the precedence is not respected.

In this simple example you'll get familiar with Verilog operators precedence and explore some corner cases.

The Verilog module is basic building block for any design. Any chip designed in Verilog is a collection of modules exchanging data.

It's time to do your first testbench and instantiate you first Design Under Test. We're moving up in the world...

A small introduction in testbench architectures. We'll use this on all the examples in this course.

Each Verilog module is simulated in a time frame. Data flows from the module's inputs to the outputs and gets plotted by the simulator in a waveform.

Generate a simple waveform and get familiar with time units and signals with four states values (1/0/X/Z).

As life taught us, almost all problems have multiple solutions. In Verilog you can describe the same behavior by using a variety of coding styles.

Discover what Structural Design is and how it can be used in Verilog.

Implement a simple circuit that calculates the sum of two bits. You also get to implement the testbench for it.

Discover what Dataflow Style is and how it can be used in Verilog.

Implement a simple circuit that calculates the sum of two bits. You also get to implement the testbench for it.

Discover what Behavioral Style is and how it can be used in Verilog.

Implement multiple Verilog procedures and see how they are executed in parallel.

Implement a simple circuit that calculates the sum of two bits. You also get to implement the testbench for it.

Let's design an 1bit FULL ADDER using all 3 Verilog coding styles.

Implement a simple circuit that calculates the sum of two bits and a carry using the Structural style. You also get to implement the testbench for it.

Implement a simple circuit that calculates the sum of two bits and a carry using the Dataflow style. You also get to implement the testbench for it.

Implement a simple circuit that calculates the sum of two bits and a carry using the Behavioral style. You also get to implement the testbench for it.

Let's design a 4bit FULL ADDER using all 3 coding styles!

Implement a simple circuit that calculates the sum of two 4bit inputs and a carry using the Structural style. You also get to implement the testbench for it.

Implement a simple circuit that calculates the sum of two 4bit inputs and a carry using the Dataflow style. You also get to implement the testbench for it.

Implement a simple circuit that calculates the sum of two 4bit inputs and a carry using the Behavioral style. You also get to implement the testbench for it.

Discover Verilog Structural design.

What are Verilog built-in primitives and how to use them.

Play with all Verilog built-in primitives.

This simple circuit is present in ALL modern chips that exist on land, air and sea. Find out more!

Implement an 1bit multiplexer and a testbench for it, using Verilog.

It does the opposite as a multiplexer does. Find out more!

Implement an 1bit de-multiplexer and a testbench for it, using Verilog.

Meet a circuit with 3-state logic (has the values 0, 1 or Z (high impedance)).

Implement a tri-state buffer and a testbench for it, using Verilog.

Check out how to use tri-state buffers for implementing multiplexers

Implement a 1bit multiplexer using tri-state buffers and a testbench for it, using Verilog.

A simple circuit used to compare binary numbers. Find out more!

Implement a 1bit comparator and a testbench for it, using Verilog.

Discover the basics of combinational logic. It's simple because it's made out of logic gates.

Continuous assignments are the easiest way to describe a combinational logic expression. Find out more!

Your first example of combinational logic using continuous assignments.

An adders tree is a very popular circuit used in digital signal processing. Check out its trivial implementation using continuous assignments.

Verilog procedural assignments are used to describe complex combinational behavior. Find out more!

Implement the same adder tree circuit with procedural assignments!

Basic theory about a Nbit adder. It couldn't get easier than this!

Implement a Nbit parameterizable adder using procedural assignments. The code is also synthesizable.

Implement a Nbit parameterizable comparator using procedural assignments. The code is also synthesizable.

Some basic notions about binary encoders and decoders. Find out more!

Implement a Nbit parameterizable binary decoder using procedural assignments. The code is also synthesizable.

Find out how multiple binary Nbit decoders can be used to build larger binary decoders.

Implement a 4to16 binary decoder using two 3to8 binary decoders. This code is also synthesizable.

After implementing several binary decoders, now it's time to implement a binary encoder.

Master the basics of priority encoders.

Implement a 4to2 priority encoder using if-else-if statements. This code is also synthesizable.

Implement a 4to2 priority encoder using the case statement. This code is also synthesizable.

The basics of M x Nbit multiplexers using the Verilog behavioral style.

Implement in Verilog a 4xNbit multiplexer using the behavioral style. The design is parameterizable and synthesizable.

The basics of M x Nbit demultiplexers using the Verilog behavioral style.

Implement in Verilog a Nbit x4 demultiplexer using the behavioral style. The design is parameterizable and synthesizable.

The Seven Segment Display decoder is a very popular digital circuit present on most electronics around us. Find out more!

Implement in Verilog a 7segment decoder using the behavioral style. The design is synthesizable.

Find out the basic principles behind digital circuits used to perform mathematical operations between multi-bit inputs.

Implement in Verilog an Nbit Arithmetical Logical Unit using the behavioral style. The design is synthesizable.

Find out what sequential logic is, and how it can be implemented in Verilog.

Generate 3 clock signals using different coding styles.

Find out what edge-triggered logic and level-triggered logic are!

A D-latch and the Verilog code for it.

A D-latch with reset_n and the Verilog code for it.

Discover the D Flip Flop and how this digital circuit works!

The Verilog code for a D Flip Flop with synchronous reset_n.

The Verilog code for a D Flip Flop with asynchronous reset_n.

A very popular type of sequential circuit that can be used for transferring and storing data. Find out more!

Implement a Parallel In Parallel Out shift register in Verilog!

Implement a Serial In Parallel Out shift register in Verilog!

Implement a Serial In Serial Out shift register in Verilog!

Implement a Parallel In Parallel Out shift register in Verilog!

Discover a shift register that can be loaded with data and next shifted left or right.

Find out how Linear Feedback shift Registers can be used as a pseudo random number generators.

Implement a 16bit Linear Feedback Shift Register using Verilog.

Find out how synchronous digital counters work!

Design a parameterizable Nbit synchronous counter using Verilog!

Design a parameterizable Nbit up/down synchronous counter using Verilog!

Design a parameterizable modulo-N synchronous counter using Verilog!

A popular digital circuit used to divide the input clock with a certain ratio. Find out more!

Create a clock divider by powers of two using Verilog!

Implement in Verilog a custom digital circuit used to divide an input frequency by a factor of 3.

Discover what a Verilog function is!

Make a function that returns the sum of to 8bit numbers.

Make a function that compares if two 32bit integer numbers are equal..

Find out what a recursive function is, and how you can use it!

Make a function that computes Factorial(N).

Make a function that computes Fibonacci(N).

Design a Nbit synthesizable comparator using a function.

Discover what a Verilog task is!

Create a Verilog task used to convert from meters to feet!

Create a task able to control an 8bit shift register using Verilog. The task can load the register with data and it can control it to shift left or right.

Our Verilog code seems to look more like software. Find out why!

Create a buggy PIPO shift register and a Verilog task that will find that bug and save the day!

Find out the basics of automated verification and self-checking tests.

Create a self-checking testbench for an ALU that can perform 9 distinct operations. The ALU has a functional bug and our testbench will find it!

Find out more about these microelectronic circuits present in our everyday live! The data from your laptop, your phone, and all the cool Internet apps pass through Semiconductor Memory at some point...

Implement a simple SRAM device with 1 address bus, 1 synchronous data_write bus, and 1 asynchronous data_read bus. This code is synthesizable in FPGA devices or it can be used as a behavioral model for ASIC verification.

Implement a simple SRAM device with 1 address bus, 1 synchronous data_write bus, and 1 synchronous data_read bus. This code is synthesizable in FPGA devices or it can be used as a behavioral model for ASIC verification.

Implement a simple SRAM device with 1 address_write bus, 1 synchronous data_write bus, 1 address_read bus, and 1 asynchronous data_read bus. This code is synthesizable in FPGA devices or it can be used as a behavioral model for ASIC verification.

Implement a simple ROM device with 1 address_read bus, and 1 synchronous data_read bus. This code is synthesizable in FPGA devices or it can be used as a behavioral model for ASIC verification.