Verification Series 8 : Code Coverage with Vivado 2024.1

Explain how statement coverage measures executed executable RTL lines in Verilog, using testbench stimulus to show which lines are hit and which remain uncovered.

Hit every executable line to achieve statement coverage in vivado 2024.1. Add explicit comments for intended unused rtl code and adjust the testbench to cover all cases.

Exclude synthesis or simulation specific RTL from code coverage using conditional compilation, pragmas, and explicit comments in Vivado 2024.1, preserving debugging and legacy code.

Identify what statement coverage does not track, such as non-executable declarations like wire, rag, and logic, plus ifdef blocks and pragmas; ensure executable statements run at least once during simulation.

Discover the limitations of statement coverage: it cannot verify all input combinations or conditions and does not track branch execution, risking false full coverage, as shown by a mux example.

Understand the limitations of statement coverage, including missing input scenarios, untracked values, and unseen FSM transitions, and compare with line coverage and report insights in Vivado 2024.1.

Demonstrate 2:1 mux with a single-bit select and inputs A and B. Use a testbench and simulation to verify behavior and enable statement coverage, exporting exim coverage HTML with 96%.

Shows how to assess statement coverage in a testbench, achieving 67% and guiding steps to reach 100% by adding stimulus for select equals zero and re-running simulations.

Master branch coverage by ensuring logical paths of if, case, and ternary branching are exercised at least once. Apply stimulus to cover enable, select, and default paths in synthesizable rtl.

Demonstrates verifying a mux with an if block using a testbench, enabling branch and statement coverage in Vivado 2024.1 and generating the html report showing 100% branch coverage.

Demonstrates achieving 100% statement coverage by executing all statements, refactors to a ternary-based continuous assignment, tests a single path, and exports coverage data to an html file.

Explore why continuous assignments do not show in statement coverage and how always blocks generate events that enable coverage tools to sample updates, revealing branch coverage gaps.

Apply condition coverage to verify each subpart of a complex boolean expression evaluates to both true and false, and use a test bench to refine branch coverage.

Compare statement, branch, and condition coverage using a simple test bench, showing how each approach tests different boolean paths and ensures comprehensive verification.

This lecture explains condition coverage by independently evaluating subparts such as select and enable, showing true/false outcomes cover combinations while some zero zero cases may be missed.

Compare MCC and MC/DC in Vivado 2024.1; MCC exhaustively tests subparts, while MC/DC ensures each condition independently changes the outcome. The notes indicate Vivado supports condition coverage and branch comparison.

Demonstrate a two-input four-bit example, verify branch and condition coverages in a Verilog testbench, and compare boolean expressions with and without subparts, using simulation in Vivado 2024.1.

Demonstrates achieving 100% condition, statement, and branch coverage by testing true and false for a greater than five and b less than six, with simulation and html export via tcl.

Explore condition coverage and evaluation count in Vivado 2024.1, illustrating how short-circuiting with and/or operators affects which expressions the simulator evaluates in reading report P1.

Demonstrate short-circuit evaluation of and/or operators and how green coverage marks show fully covered combinations. Export the coverage database to HTML to compare condition coverage and branch coverage.

Understand how toggle coverage ensures every input and output bit toggles at least once in simulation, revealing rising and falling edges and potential bus width issues.

Identify how toggle coverage reveals fixed inputs, unconnected ports, plus width mismatches, guiding synthesis decisions. Recognize when all ports fail to toggle, indicating signal length mismatches or untested input combinations.

Explore toggle coverage through a simple multiplier design, enable toggle coverage in Vivado 2024.1, run a simulation with random transactions, and verify 100% coverage across 16 bits.

Understand how toggle coverage in vivado 2024.1 excludes output wires to avoid duplicate coverage by routing outputs through a temporary reg. Interpret 0→1 and 1→0 toggle statuses to assess stimulus.

Explore how toggle coverage in Vivado 2024.1 shows only the LSB two bits toggle, revealing a bus width mismatch and the impact of removing a reset.

Discover how toggle coverage analyzes a four-bit stimulus bus, showing 0 to 1 and 1 to 0 toggling, revealing unconnected upper bits, reset transitions, and 50% coverage.

Understand how to verify FSM coverage by ensuring all states are reached and all legal transitions occur, and note that Vivado lacks FSM coverage, requiring functional coverage over code coverage.

Explore functional coverage basics: beans, cover points, and cover groups. Learn to sample values on a clock edge and cover ALU data, operation, and FSM coverage in Vivado 2024.1 testbench.

Explore a three-state Verilog FSM flowchart with an active-high reset, idle, s0, and s1, and learn to add a functional coverage matrix in a testbench.

Build a test bench with a cover group for functional coverage to track an fsm's states using clock-driven stimulus and reset sequences, reporting coverage per instance.

Build and monitor a testbench cover group for state transitions, tracking valid and illegal transitions between S0, S1, and ideal states with reset behavior to ensure finite state machine coverage.

launch a simulation to generate a coverage database and export html reports in vivado. run write xim coverage to update databases and analyze state, transition, and fsm coverage.