
Learn how code coverage may reach 100% yet miss input and output combinations; use functional coverage to test combinations and apply assertions to catch incorrect behavior in the verification environment.
Learn how to use Vivado to generate coverage reports during simulation, including setting the coverage name and directory, and selecting coverage types such as line, branch, condition, or toggle.
Learn how to generate a coverage report in Vivado 2024.1, configure coverage options, run simulations, and convert coverage data to readable HTML.
Hit every executable line to achieve statement coverage in vivado 2024.1. Add explicit comments for intended unused rtl code and adjust the testbench to cover all cases.
Demonstrate 2:1 mux with a single-bit select and inputs A and B. Use a testbench and simulation to verify behavior and enable statement coverage, exporting exim coverage HTML with 96%.
Explore how toggle coverage in Vivado 2024.1 shows only the LSB two bits toggle, revealing a bus width mismatch and the impact of removing a reset.
Discover how toggle coverage analyzes a four-bit stimulus bus, showing 0 to 1 and 1 to 0 toggling, revealing unconnected upper bits, reset transitions, and 50% coverage.
Explore functional coverage basics: beans, cover points, and cover groups. Learn to sample values on a clock edge and cover ALU data, operation, and FSM coverage in Vivado 2024.1 testbench.
Explore a three-state Verilog FSM flowchart with an active-high reset, idle, s0, and s1, and learn to add a functional coverage matrix in a testbench.
In modern digital design verification, code coverage plays a critical role in ensuring the quality and completeness of simulation-based testing. It is especially significant in safety-critical and regulated industries such as aerospace and avionics, where verification must meet strict compliance standards like DO-254. DO-254 mandates that hardware designs undergo rigorous verification processes, and code coverage is a key metric to demonstrate that all parts of the RTL have been exercised and tested. This helps identify untested portions of the design, ensuring that no functionality is left unchecked during simulation.
This course offers an in-depth exploration of code coverage using Vivado, with a strong emphasis on practical learning. It covers every essential aspect of the coverage workflow—from understanding the purpose and types of code coverage to generating and analyzing coverage reports in Vivado. The course clarifies the differences between code coverage, functional coverage, and assertions, helping learners understand how these elements complement each other in a comprehensive verification strategy.
Learners will explore five main types of code coverage: Statement Coverage, which checks whether each line of code has been executed during simulation; Branch Coverage, which ensures all control flow branches have been taken; Condition Coverage, which verifies each boolean condition within decision statements; Toggle Coverage, which tracks the transitions of signals to confirm full activity; and FSM (Finite State Machine) Coverage, which ensures all states and transitions in a state machine are exercised.
Through step-by-step demonstrations, students will learn how to design testbenches, write RTL code, simulate with Vivado, and interpret coverage results. 80% of the course is focused on code and flow demonstrations, 12% covers the theoretical foundations, and 8% involves self-check assignments to reinforce logical reasoning and understanding.
By the end of this course, learners will not only understand the theory behind code coverage but also gain practical experience using Vivado to achieve coverage closure in real-world verification environments, making it ideal for professionals working under compliance-driven standards like DO-254.