UVM in Systemverilog -2: Writing Re-usable Agents
4.0 (20 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
310 students enrolled

UVM in Systemverilog -2: Writing Re-usable Agents

Look and feel of Profession UVM Agent in complex verification environments & VIPs
4.0 (20 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
310 students enrolled
Created by Ajith Jose
Last updated 10/2019
English
Current price: $34.99 Original price: $49.99 Discount: 30% off
5 hours left at this price!
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This course includes
  • 2 hours on-demand video
  • 3 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Universal Verification Methodology (UVM) in Systemverilog
  • Writing complete reusable UVM Agent
Requirements
  • Basic level understanding on UVM Methodology
Description

This is an intermediate level course in Systemverilog HDL focusing only the 'Universal Verification Methodology' (UVM) in it.  The objective of this course is to make UVM learning more comfortable on this industry demanding topic.

The primary targets of  of this course are the VLSI aspirant students and verification engineers. This will give enough confidence to write a complete UVM agent that have the look and feel of any professional UVM based verification environment or VIP. Apart for verification people,  designers and managers who want to get a feel of a UVM Agent are encouraged to enrol this course.

Inside the course, you will get a quick overview of UVM test bench and the idea of a reusable UVM agent in any verification environment. The major portion of this course is a code walk through over a UVM agent. First you will setup a dummy DUT and sample test bench. Next you will be going over the process of writing master-driver, slave driver, monitor, coverage collector and a reusable interface level agent step by step. You will go through the code of write-address, write-data, write-response, read-address, read-data agents which corresponds to the five channels of a standard AXI protocol communicator. Finally, you will also learn how to write the top level AXI agent which will be a container for all 5 agents, and to configure them to act as a master, slave or passive agent.

To  make this course effective for you, you must have the basic knowledge of using Systemverilog and UVM. This course is designed as a continuation of the the beginner level UVM course " UVM in Systemverilog : Quick start for absolute beginners". Also having basic level understanding of Object Oriented  Programming concepts will make this course a little more effective for you.

If you are already familiar with UVM and have sufficient knowledge in writing a standard UVM agent and test-bench, then this course is not for you.

Who this course is for:
  • Verification Engineers & Students with some understanding of the methodology
  • Those who want to know how a UVM agent will look like in a professional UVM based TB & in VIPs
Course content
Expand all 16 lectures 02:04:17
+ Code Walk through - 1 : Do the pre-setups
3 lectures 26:07
Setup a dummy DUT
09:53
Writing Testbench and Configs
11:00
Writing AXI Transaction
05:14
+ Code Walk through - 2 : Writing Reusable Agent
7 lectures 01:14:42
Writing Master Driver
10:57
Writing Slave Driver, Monitor and Coverage Component
10:34
Writing a complete Interface Agent ( Write Address Agent)
10:56
Writing Write-Data & Write-Response Agents
09:36
Writing Read-Address & Read-Data Agents
06:03
Writing AXI Protocol Scoreboard & Coverage Components
11:03
Writing Top-level AXI Agent sing 5 Channel Agents
15:33