This is an intermediate level course in Systemverilog HDL focusing only the 'Universal Verification Methodology' (UVM) in it. The objective of this course is to make UVM learning more comfortable on this industry demanding topic.
The primary targets of of this course are the VLSI aspirant students and verification engineers. This will give enough confidence to write a complete UVM agent that have the look and feel of any professional UVM based verification environment or VIP. Apart for verification people, designers and managers who want to get a feel of a UVM Agent are encouraged to enrol this course.
Inside the course, you will get a quick overview of UVM test bench and the idea of a reusable UVM agent in any verification environment. The major portion of this course is a code walk through over a UVM agent. First you will setup a dummy DUT and sample test bench. Next you will be going over the process of writing master-driver, slave driver, monitor, coverage collector and a reusable interface level agent step by step. You will go through the code of write-address, write-data, write-response, read-address, read-data agents which corresponds to the five channels of a standard AXI protocol communicator. Finally, you will also learn how to write the top level AXI agent which will be a container for all 5 agents, and to configure them to act as a master, slave or passive agent.
To make this course effective for you, you must have the basic knowledge of using Systemverilog and UVM. This course is designed as a continuation of the the beginner level UVM course " UVM in Systemverilog : Quick start for absolute beginners". Also having basic level understanding of Object Oriented Programming concepts will make this course a little more effective for you.
If you are already familiar with UVM and have sufficient knowledge in writing a standard UVM agent and test-bench, then this course is not for you.