Verification Series Part 5: UVM RAL Essentials

Explore the register block in a verification environment, learning how it tracks addresses for registers and memories in a DUT, and implement the register block for existing registers.

Build a register block with a base address and two 32-bit registers at offsets 0 and 4, then implement reg_one and reg_two in the verification environment using UVM_reg.

Extend UVM_reg_block to create top_R_Block, register with UVM_OBJECT_UTILS in the factory, and add reg_one_instance and reg_two_instance for reg_one and reg_two; use build() and configure() with UVM_NO_COVERAGE.

Create a register address map using default_map with base address zero and 32-bit little-endian bus. Add_reg at offsets zero and four with RW and R options, then lock the model.

Learn how to bridge register transactions to bus transactions with an adapter, using reg_to_bus and bus_to_reg, and implement an APB-based adapter for a memory interface in a verification environment.

Learn how an adapter converts reg transactions to bus transactions so a DUT can receive random stimulus with burst transactions through its input and output ports.

Understand the reg sequence flow by using write and read methods with status and data, using the address map, converting to reg transactions, then to bus transactions toward the DUT.

Examine the six data members of the UVM reg bus op structure—address, data, kind, optional fields, and status—and how a sequence updates them before bus transaction conversion.

Execute the full flow from reg to bus and back, using reg-to-bus and bus-to-reg adapters to convert transactions and update the reg model through driver, monitor, and predictor.

Master how UVM reg write and read methods convert register transactions to burst bus transactions using reg to bus, guided by address maps and status updates.

Understand how bus2reg converts a bus transaction (write address and dout) into a reg transaction (kind, data, address) to drive the reg model and update mirror and desired value.

Develop an adapter in a verification environment for a native memory interface with clock, reset, write, address, DIN, and DOUT ports; translate reg to bus transactions for write and read.

Map bus to reg transactions with a bus-to-reg adapter, casting burst items to transactions and setting rw kind to UVM write or read, then align address and data.

Explore implementing an APB protocol adapter by extending the uvm reg adapter to support reg-to-bus and bus-to-reg transactions, with an enum-driven driver signaling pselect, pwrite, and pready.

Develop adapter code with protocol specific ports to translate bus to reg transactions, casting bus items to the transaction class and updating RW, address, data, and status for APB read/write.

Write a register by providing the transaction status and value; reg to bus converts it to a bus transaction, and a monitor samples reads with a predictor translating burst transaction.

Understand predictor types in uvm verification, sample the dut response, update the register model, and explore reg class methods such as set, get, predict, mirror, write, read, get_mirror_value, and reset.

Explore implicit prediction in a register model where auto prediction updates mirror and desired values from the driver's response, without an explicit predictor, via bidirectional TLM ports.

Learn how explicit predictors fit into a verification environment, where a register model generates transactions via adapter, sequencer, and driver to a dut, with predictor updating desired and mirror values.

Explore passive predictor in UVM reg class, sampling bus sequences to update desired and mirror values without generating reg transactions, alongside implicit and explicit predictors.

Build a UVM verification environment linking sequence, sequencer, and driver to validate bidirectional TLM ports with a register model. Randomize data, apply stimuli, and verify responses without a DUT.

Analyze a simple 8-bit register in a dut with write and read paths. Build a verification environment that handles clock, reset, and single-address access.

Build a verification environment by adding a driver and sequencer in UVM RAL essentials, using a transaction class and factory to drive the dut.

Register a UVM agent class to the factory and instantiate the built-in sequencer and driver. Connect their TLM ports and export ports to complete the agent setup.

Implement an 8-bit register model in UVM by building a register field, configuring it, creating the reg block and adapter, and mapping read/write access.

Create and connect a verification environment by building reg model, adapter, and agent, configure address maps, set sequencer paths, and run a UVM test with a testbench top.

Show how commenting out code affects the console messages, including include_coverage status, replace deprecated set_config with uvm_config_db, and extend the register model with sequences.

Explore how a uvm reg class uses desired and mirror values, reset and randomization states, and AIS methods to manage register transactions with the DUT.

Explore UVM register methods for the desired and mirror variables, including set, get, and get_mirrored_value. Learn front-door versus backdoor access and how transactions update both values.

Extend a uvm sequence to work with a reg block, using get, set, and update to manage the 8-bit desired and mirror values during DUT transactions.

Explore mirroring values by comparing the desired and mirror variables, using the set and update methods, and enabling implicit prediction with set_auto_predict(1) in the register map to reflect DUT state.

Learn how predict updates both mirror and desired register values, and how mirror performs a read transaction on the DUT to update values and check for mismatches with UVM_CHECK errors.

Demonstrate the sequence of write, get, get_mirrored_value, and predict, then mirror with UVM_CHECK or UVM_NO_CHECK to compare read data against mirror and desired values from the register model and DUT.

Perform a single write to a DUT register, updating the desired and mirror values via reg predict method. Then read the register to observe data and waveform updates (d_in, d_out).

Explore how to perform five random read and write transactions to the DUT using a for loop, generating values with $urandom/$random/$random_range, writing and then reading to verify data.

Use the randomized method to generate random values for a reg field, access the value via the value variable, and write them to the DUT for 10 transactions.

Explore the four reset methods—has_reset, get_reset, set_reset, and reset—in the register model, used in the verification environment to configure, retrieve, modify, and reset values without touching hardware.

Demonstrates using UVM RAL to inspect and manipulate a register's reset value, including has_reset, get_reset, set_reset, and applying reset while comparing mirror and desired values in a verification environment.

Demonstrate how the reset method drives the DUT with an independent reset sequence, synchronize the register model to 0x11, apply and release reset, and verify mirrored values align.

Explore front-door and back-door access concepts in verification, and learn how to implement them in your environment, including the remaining back-door methods: peek and poke.

Compare front-door and backdoor register access and learn peek and poke for backdoor operations. Front-door read and write require valid transactions with clock, reset, address, and data signals.

Explore backdoor access in UVM RAL by specifying the register path to directly read and write internal registers without valid port signals, unlike front-door access.

Demonstrates front-door access for an 8-bit register, detailing configure, build, and map steps, explicit front-door path usage with uvm_frontdoor for write and read, and distinguishing front-door from backdoor access.

Master backdoor access by building RTL paths with add_hdl_path and add_hdl_path_slice to reference dut.reg1 in the top system, including a child module s1.

Demonstrates enabling backdoor access in a UVM RAL workflow by adding the +W switch, configuring a DUT register, and performing front-door and backdoor read/write operations.

Learn how to use poke for writing and peek for reading in backdoor access to a register, including setup steps, rtl paths, and verifying desired versus mirror values.

Observe a write operation that updates both the desired and mirror values to 15, followed by a read returning 15, and reveals backdoor access without valid input signals.

Introduce the fundamentals of an explicit predictor, using it to sample the DUT response. Demonstrate how an explicit predictor simplifies coverage computation with a typical register example.

Develop an explicit prediction within the register model to enable coverage, using the inbuilt predictor and default map, with the adapter producing burst transactions for sequencer, driver, and dut interface.

Build and verify a UVM environment with a driver, monitor, scoreboard, and agent. Apply stimuli through an interface, handle write/read transactions, and check DUT responses.

Extend a uvm reg class to build a register model, map an 8-bit temp field at base zero, and drive a five-transaction reg sequence with reg-to-bus adapters.

Add an agent with a sequencer, driver, monitor, reg block, adapter, and predictor, then build and connect components via tlm ports to scoreboard and default map at base address zero.

Instantiate environment and sequence in build phase, raise and drop objections, apply a drain time of 20, connect interface to the DUT, generate clock, and configure predictor via uvm_config_db.

Testing code demonstrates driving a write to the DUT, monitor and scoreboard validation, explicit predictor updates to the register model, and a read operation that confirms a test pass.

Learn to perform coverage analysis for a register model with UVM RAL by creating a tempore cover group for an 8-bit field, specifying cover points and using sample value methods.

Configure targeted coverage in a reg block by using UVM_NO_COVERAGE by default, then enable UVM_CVR_FIELD_VALS for selected registers, build and map them, and run a run.do to view console coverage.

Run the testbench with the run.do Tcl file to compute coverage for register fields, learn to implement coverage by adding cover points and sample and sample_value in the reg class.

Use coverage analysis of a register to establish fundamentals for a verification environment, implement the register block for memories, and explore single and burst memory transaction methods and coverage strategies.

Explore building a simple 16x8 memory within the uvm ral, using a 4-bit address and 8-bit din/dout, with clocked writes via non-blocking assignments and a dout output for verification.

Define an explicit predictor for memory in a UVM environment, avoiding desired and mirror values, and implement driver, monitor, scoreboard, and agent to verify read and write transactions.

Learn to build a memory and register model in uvm by implementing uvm_mem and uvm_reg, registering with the factory, and configuring maps and back-door paths in the verification environment.

Extend a uvm sequence to cover front-door and back-door single transactions, register the ral block to a factory, and perform write/read at address 0, with poke/peek at address 1.

Perform multiple memory transactions with a front-door access method by writing and reading 10 unique addresses, and compare results using array_write and array_read.

Master burst write and burst read in UVM RAL memory using dynamic UVM reg data arrays and get_offset, and modify adapters to handle burst transactions by mapping rw.kind to tr.WR.

Compute memory coverage by analyzing DUT stimuli in UVM RAL essentials, using single and burst transactions to cover memory addresses (16 locations with a 4-bit bus) and read/write data.

Learn memory coverage computation in a UVM RAL environment by embedding mem_cov in the monitor, using 8-bit D and D_out, 4-bit address bins, and cross coverage.

Connect the fundamentals to build a verification environment using RAL for verifying a register and memory, and gain insight into how these fundamentals verify a DUT.

Perform APB read and write transactions to a DUT with a register model, using select, write, address, and enable signals to update and retrieve 32-bit data.

Explain a dut with a top module, 1‑bit clock and reset, 32‑bit address, 32‑bit write data, five registers including a 4‑bit control, and read/write logic with offset addresses for verification.

Build a complete uvm verification environment for a dut, including driver, sequencer, monitor, scoreboard, and predictor, with a transaction class, constrained addresses, and an integrated register model.

Extend a UVM monitor with an analysis port to feed the scoreboard and predictor, and connect driver, monitor, and sequencer in an agent. Sample the DUT interface and align timing.

Create a register model for five registers, with control_R as a 4-bit read-write and reg1 to reg4 as 32-bit fields, mapped to default_map at offsets 0, 4, 8, 12, 16.

Build a uvm ral adapter and register model by mapping reg2bus and bus2reg transactions. Create sequences to read and write multiple registers in the testbench environment.

Add a testbench top by instantiating the environment and sequences for the control register, then perform five write and five read transactions with drain time 200 and run the test.

Execute an APB transaction test on an EPV to verify the DUT control register by writing five random values at address zero and reading back five, with valid APB signals.