Verification Series Part 4: UVM Projects

Extend a UVM agent to connect driver, sequencer, monitor, and scoreboard, build and connect components in the environment, and verify clock generator and UART interface.

Explain the UART receiver design, including the RX clock, start and reset signals, length and parity handling, and two stop bits, with center sampling at a 16x RX clock.

Implement a 128-location i2c slave memory that initializes on reset and uses a state machine to collect an 8-bit address (7-bit address plus operation bit) for read or write.

Explore how to verify read, write, and reset operations for memory using a uvm environment with sequences, drivers, monitors, and a scoreboard.

Explore the AB memory interface, including reset, clock select, slave enable, P enable, and 32-bit write and read data paths. Follow the four-state design: idle, setup, access, transfer.

Build a UVM testbench for an APB RAM with a config class, a constrained op_mode transaction, and sequences that exercise write, read, and error scenarios.

Explain the write data channel, including W valid/ready, W ID, and W data across four lanes with AW size and W strobe, and how W last triggers write response channel.

Explore AXI burst types—fixed, increment, and wrap—and how they determine next address. Learn increment mode by showing current address plus bytes stored, guided by W strobe.

Implement a write response channel FSM that waits for W last and B ready, computes the response from address and aw size, and asserts B valid before returning to idle.

Demonstrate tlm analysis with a simple 4-to-1 mux that selects among four 4-bit inputs A, B, C, D using a 2-bit select and outputs Y, with default zeros.

Build a UVM verification environment with an agent (driver, sequencer, monitor), connect analysis ports and exports, and validate DUT transactions with a reference model and scoreboard.