UVM for Verification Part 2 : Projects
What you'll learn
- Verification of Combinational Circuits
- Verification of Sequential Circuits
- Verification of Common Bus Protocols viz. APB, AXI
- Verification of Communication Protocols viz. UART, SPI, I2C
- Understanding usage of Virtual Sequencer, Sequence Library and TLM analysis FIFO
- Basic understanding of UVM
Writing Verilog test benches is always fun after completing RTL design. You can assure clients that the design will be bug-free in tested scenarios. As system complexity grows day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability, which help verification engineers quickly locate hidden bugs. System Verilog lags behind the structured approach, whereas UVM works hard to form a general skeleton. The addition of the configuration database shifts the way we used to work with the verification language in the past. Within a few years, verification engineers recognized the capabilities of UVM and adopted it as a de facto standard for RTL design verification. The UVM will have a long run in the verification domain; hence, learning about the UVM will help VLSI aspirants pursue a career in this domain.
This is a Lab-based course designed such that anyone with the fundamentals of UVM could understand how verification engineers use UVM to perform verification of commonly used RTLs and sub-blocks in FPGA. The course covers verification of the combinational circuit like combinational adder, Sequential circuit like Data flip-flop, communication interfaces like a clock generator, UART, SPI, and I2C, and Bus protocols like APB, AXI, and demonstration of few useful UVM concepts like a virtual sequencer, TLM analysis FIFO, and a sequence library.
Who this course is for:
- Engineers involved/interested in the verification of RTL's
I currently serve as an instructor, where my responsibilities involve creating educational content for both undergraduate and postgraduate students. This content is designed to help them grasp the latest trends in VLSI (Very-Large-Scale Integration) technology. Prior to this role, I held the position of FPGA Developer Lead at one of India's premier Financial Technology companies. There, I led a team in the development of a cutting-edge High-Frequency Trading platform, leveraging Xilinx Alveo FPGA Cards.
Before my venture into the fintech industry, I dedicated three years as a VLSI Trainer at Mumbai University, India. Additionally, I spent one year as a Research Scientist at a renowned R&D center focused on Applied Electronic Research in India. During this time, I made significant contributions to projects such as the development of a Gradient Controller and a 64 MHz Receiver on FPGA for an indigenous MRI machine.
In my leisure hours, I have a passion for creating Udemy courses, and I have also collaborated with organizations like Larsen & Toubro Technology Services and Power International. In these collaborations, I played a pivotal role in designing various FPGA-based systems, including Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS (Data Transmission Systems). My primary areas of expertise and interest revolve around Front End VLSI Design, System-on-Chip (SoC) development, and Chip Verification.