Verification Series Part 4: UVM Projects

Verify a 4-bit combinational multiplier in a single-sequence verification environment, using a driver, monitor, and scoreboard to compare Y with a*b via the mcore_if interface.

Learn to build a UVM verification environment with a transaction, generator, driver, monitor, and scoreboard to verify a multiplier using randomized A and B inputs and observed Y output.

Create a UVM verification environment for a multiplier by wiring an agent with sequencer, driver, monitor, and scoreboard, connecting TLM ports and analysis ports, and running run_test for the test.

Build and verify a D flip-flop as the first sequential circuit, implementing posedge clock with reset that clears dout, otherwise follows d, using an interface and a verification environment.

Explore how a configuration class shares parameters and selects an active or passive agent in a UVM environment. Utilize a transaction, driver, monitor, and scoreboard to validate D flip-flop behavior.

Configure a uvm agent as active or passive using uvm config db, then build an environment with driver, sequencer, monitor, and scoreboard to verify a dff.

Design a clock generator that down-converts a 50 MHz input to multiple baud rates using TX_max and TX_count counters to generate TX_clock, and verify it in a UART-focused verification environment.

Demonstrate a UVM-based verification environment for a clock generator, covering a transaction-driven sequence, driver and monitor, constrained baud values, and a scoreboard that computes clock period and baud counts.

Extend a UVM agent to connect driver, sequencer, monitor, and scoreboard, build and connect components in the environment, and verify clock generator and UART interface.

Explore the verification of a new UART by examining the clock generator driven TX and RX paths, with configurable baud rate, start bit, data length, parity, and stop bits.

Learn how a UART clock generator creates rx and tx clocks from a shared clock, with rx 16x faster to sample TX data in the middle.

Learn the uart transmitter design, covering tx clock, start and stop bits, data width and parity enable, and the tx and tx done signals; includes parity generation and state decoding.

Explain the UART receiver design, including the RX clock, start and reset signals, length and parity handling, and two stop bits, with center sampling at a 16x RX clock.

Examine the top module that coordinates a clock generator, u_rx, and u_tx for uart communication, where baud rate-driven rx and tx clocks govern data transfer.

Write a testbench to verify a dut by applying stimuli via a driver, configuring baud rate, data length, parity, and stop bits, coordinating transmitter and receiver until tx_done and rx_done.

Introduce the UART verification environment in UVM, with a config class, a constrained transaction, and sequences for baud, length, parity, and stops, plus driver, monitor, and scoreboard.

Build a verification environment with an agent, driver, sequencer, monitor, and scoreboard, and run random and fixed-length sequences rb, rb_p, and vo to verify parity and stop-bit handling.

Understand how a spi controller converts input data into spi signals to memory for write and read operations, including MOSI, MISO, chip select, ready, operation_done, and the 32-depth memory.

Explore the SPI memory flow from idle to operation, triggered by chip select low, where the bit decides read or write; writes update memory and reads fetch data from address.

Demonstrates generating a valid transaction in a verification environment by driving write and read operations to the SPI controller, updating memory at address 25 with 67 and signaling done.

Build a complete verification environment for a SPI controller using UVM concepts, including config, transaction, sequence, driver, monitor, and scoreboard.

Build and connect a UVM SPI verification environment with config, driver, sequencer, monitor, and scoreboard; run write/read sequences and verify data matches the scoreboard with native SPI signals.

Explore generating native spi signals for write and read transactions, including chip select, MISO, and MOSI, with reset high and eight data bits plus eight address bits.

Delve into spi verification in uvm part 4 by building driver, monitor, and scoreboard to verify read, write, and reset sequences for NATU memory, including 16-bit data and 8-bit address.

Set up the native spi p2 verification by connecting driver, sequencer, monitor, and scoreboard, then run 10 write and 10 read transactions with data matches.

Understand the I2C interface, including start and stop conditions, a 7-bit address with an 8th bit for read/write, and master-slave acknowledgments on SCL and SDA.

Implement a 128-location i2c slave memory that initializes on reset and uses a state machine to collect an 8-bit address (7-bit address plus operation bit) for read or write.

Explore the i2c master controller by generating the start condition, forming the address with operation type, sending data for writes or reading data with acknowledgment and a shift register.

Understand the typical write and read transactions to a DUT by applying the correct waveform, address, and data, asserting WR as needed and waiting for the done signal.

Explore how to verify read, write, and reset operations for memory using a uvm environment with sequences, drivers, monitors, and a scoreboard.

Create a UVM verification environment by adding driver, sequencer, monitor, agent, and scoreboard; connect ports, build test and environment classes, and execute reset, write_data, and read_data sequences in the testbench.

Explore APB memory fundamentals, including setup, access, and ready states, as you learn how write and read operations use address, data, and the slave select and ready signals.

Explore the AB memory interface, including reset, clock select, slave enable, P enable, and 32-bit write and read data paths. Follow the four-state design: idle, setup, access, transfer.

Explore how typical transactions appear in waveform, guiding driver development for a verification environment; see write and read flows, ready signaling, and SLV error handling in a 32-element, 32-bit memory.

Build a UVM testbench for an APB RAM with a config class, a constrained op_mode transaction, and sequences that exercise write, read, and error scenarios.

Learn to implement a complete uvm verification environment with driver, monitor, scoreboard, and agents that drive and observe a dut via a sequencer and an interface.

Explore the ABP_RAM P3 verification in UVM projects by driving 15 write and read transactions, handling P select, enable, and ready signals, and validating memory updates with a scoreboard.

Understand AXI interface fundamentals and its five channels—write address, write data, write response, read address, and read data—for memory read and write transactions.

Examines the AXI write address channel, detailing AW valid, AW ready, AW ID, AW length, AW size, AW address, and AW burst, and explains fixed, increment, and wrap burst modes.

Explain the write data channel, including W valid/ready, W ID, and W data across four lanes with AW size and W strobe, and how W last triggers write response channel.

Describe the AXI write response channel flow: using B ready and B valid to exchange the B response after a write transfer, with B response values 00, 10, or 11.

Explore axi write transactions across address, data, and response channels, detailing aw valid, aw address, aw id, length, size, burst, w valid, w data, w last, and b response.

Initialize FSM modules for the write address channel, the write data channel, and the response channel, driven by AW valid, W ready, and B ready to update memory and respond.

Explore AXI burst types—fixed, increment, and wrap—and how they determine next address. Learn increment mode by showing current address plus bytes stored, guided by W strobe.

Explore fixed mode in burst type p2, where the address remains constant across eight transactions and data varies, and compare to increment mode and its sensor applications.

Learn how wrap mode calculates the wrap boundary from AW size and burst length, then derive the next address using modulus arithmetic and update memory across a burst sequence.

Explain the write data channel by outlining the data FSM and the response FSM, including idle, ready, valid, address decoding, and how first and the address bus govern memory updates.

Implement a write response channel FSM that waits for W last and B ready, computes the response from address and aw size, and asserts B valid before returning to idle.

Understand the AXI read channel, including AR valid, AR id, length, size, and burst type. See how R valid, R data, and R last deliver responses, unlike the write channel.

Analyze the read channel architecture, covering the read address and read data channels, AR valid/ready, and R valid with R last for burst reads, with address sampling.

Build a UVM verification environment for memory. Create a multi-channel transaction class with aw_valid, aw_id, ar_id, and develop fixed, increment, wrap, and error modes, plus a driver-driven run phase.

Explore how a uvm monitor stores write data in a 32-bit array and validates read data using aw valid, w ready, b valid, ar valid, and r valid signals.

Build a verification environment with a driver, sequencer, and monitor connected to the DUT via an interface and clocks. Run reset, fixed mode, wrap, and increment transactions with zero errors.

Build a sequence library in UVM to automatically select and execute sequences for transactions. Define a transaction class and register it to the factory, then add sequences to the library.

Connect the driver and sequencer via the agent, integrate a sequence library in the environment and test, and configure modes UVM_SEQ_LIB_RAND, UVM_SEQ_LIB_RANDC, SEQ_LIB_ITEM, and SEQ_LIB_USER with min and max counts.

Learn how a UVM TLM FIFO prevents packet loss when a sender and receiver run at different rates, with configurable depth and put_export and get_export ports.

Demonstrate implementing a UVM sender and receiver with a TLM FIFO, using blocking put and get ports to transfer logic [3:0] data, five transactions at 20 ns, receiver operates slower.

Demonstrate tlm analysis with a simple 4-to-1 mux that selects among four 4-bit inputs A, B, C, D using a 2-bit select and outputs Y, with default zeros.

Explore a UVM verification environment where driver and sequencer send stimuli through interface, while monitors and a scoreboard use analysis export to compare DUT responses with reference data for pass/fail.

Define a UVM verification environment with a transaction class, rand inputs, and a case-based reference model. Integrate a driver, monitor, and scoreboard using an analysis fifo for data comparison.

Build a UVM verification environment with an agent (driver, sequencer, monitor), connect analysis ports and exports, and validate DUT transactions with a reference model and scoreboard.