Verification Series Part 3: UVM Essentials

Learn how UVM verbosity levels control what prints to the console, from none to bug, using get and set report verbosity level on the default UVM top, with practical examples.

Learn to adjust UVM reporting severity by using set report severity override for a class and set report severity ID override for individual IDs, converting fatal events to errors.

Learn to modify macro actions in UVM by overriding sev actions with set_report_severity_action, combining actions like UVM_DISPLAY, UVM_NO_ACTION, and UVM_EXIT, and observing their effects on console output and simulation control.

Explore how UVM builds verification environments with static components, dynamic transactions, a UVM tree, and phases, using UVM objects and components to drive drivers, monitors, and scoreboards.

Learn how the UVM compare method checks if two objects have identical data, returning 1 when equal and 0 otherwise, using two instances, randomization, and a copy to force equality.

Use the create method to instantiate UVM objects, enabling factory-based type overriding. The lecture demonstrates F1 and F2 creation with type_id::create, path arguments, randomize, and print to verify object creation.

Implement the do_compare method in UVM for field-by-field equality, using cast and temp access, and verify with two objects o1 and o2 via do_print/do_copy references.

Classify phases into time-consuming and non-time-consuming categories, noting that timed phases use tasks with timing constructs while non-timed phases use functions and require overriding with super.

Explore two uvm phase classifications: time-consuming phases (task methods, no super) and non-time-consuming phases (functions, with super), plus the construction, run, and cleanup phases and how to override them.

Override UVM phases by using functions for non-time consuming phases and tasks for time-consuming ones, calling super when needed, focusing on build, connect, end of elaboration, start of simulation, and run.

Explore fundamentals of UVM essentials, including sequencer-driven test benches, drivers, interfaces, and DUT interactions, with transaction-level modeling and blocking, non-blocking put, get, and transport operations.

Learn to add a blocking put implementation in the consumer, connect the export to the implementation, and establish the endpoint so producer data reaches the consumer without fatal errors.

Explore the uvm analysis port for one-to-many data broadcast from a producer to multiple subscribers, using a write implementation and connect phase to link port to consumers.

Explore fundamentals of sequence in UVM verification: from sequences and sequencers to drivers and interfaces, applying TLM put to DUT for write, read, and address-range test cases.

Design a transaction and sequence in uvm, connect sequencer, driver, and monitor inside an agent, and wire them into an environment with a scoreboard for dut verification.

Examine how a uvm verification environment uses a transaction class and three methods with sequences to send multiple transactions through a driver and sequencer, noting default behavior.

Override the default arbitration by setting the arbitration method to uvm_seq_arb_strict_fifo, demonstrate priority between sequences 1 and 2, and show how higher priority holds the sequencer until completion.

Commenting out priority switches to the default fifo, the lock method then lets a single sequence complete all three transactions before others gain sequencer access.

Register the test class to the factory, add a sequence named gen and an environment in build, then raise and drop an objection to start gen via e.agent.sqr.

Compare combinational and sequential adders and implement a sequential adder in Verilog, using a 4-bit A and B input, a 5-bit Y output, and a clocked, synchronous reset.

Register the driver class with the UVM factory, access the interface, and store sequencer data in a data container; reset the DUT and process items every two clock ticks.