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FPGA USB Device Design in VHDL - From First Principles
Rating: 4.7 out of 5(5 ratings)
32 students

FPGA USB Device Design in VHDL - From First Principles

Building a FIFO-Based FPGA USB CDC Interface in VHDL Without Vendor IP Cores
Created byL Athukorala
Last updated 6/2026
English

What you'll learn

  • Understand the USB architecture from a hardware and protocol perspective
  • Implement a USB CDC (Communications Device Class) interface entirely in VHDL
  • Create and manage USB descriptors, including device, configuration, interface, and endpoint descriptors
  • Design control transfer handling for USB enumeration
  • Implement bulk IN and OUT endpoints for data communication
  • Build FIFO-based data paths between USB endpoints and internal FPGA logic
  • Design robust finite state machines for USB packet handling and flow control
  • Handle USB data buffering, handshaking, and error conditions
  • Debug USB communication using simulation and real hardware testing using Signal Tap Logic Analyser
  • Structure a medium-sized VHDL project for clarity, reuse, and maintainability

Course content

1 section • 93 lectures • 28h 8m total length

  • Introduction8:56
  • Where to Get the FPGA Explorer Development Board0:05
  • Course Roadmap5:26
  • Transmitter Intro29:47
  • Transmitter Block Diagram6:14
  • Transmitter Signalling9:03
  • CRC 16 Circuit26:06
  • CRC 16 VHDL32:12
  • Shift Register VHDL36:45
  • Transmitter Top Level Timing Diagram26:18
  • Transmitter VHDL 110:51
  • Transmitter VHDL 215:47
  • Transmitter VHDL 313:22
  • Transmitter VHDL 46:22
  • Transmitter VHDL 517:33
  • Transmitter VHDL 69:30
  • Transmitter VHDL 79:02
  • Transmitter VHDL 818:02
  • Transmitter VHDL 933:54
  • Transmitter Test Bench 119:03
  • Transmitter Test Bench 224:48
  • Receiver Overview13:31
  • Sync Module Design6:19
  • Rx Sampler 122:31
  • Rx Sampler 225:38
  • Rx Sampler 319:35
  • Rx Sampler 415:20
  • Receiver Design 127:14
  • Receiver Design 231:57
  • Receiver Test Bench15:33
  • Types Of USB Transfers12:46
  • USB Transfer Flow11:56
  • USB Packets12:51
  • USB Transfer Examples12:11
  • Configurations, Interfaces and Endpoints16:50
  • Descriptor ROM VHDL7:00
  • Device Descriptor17:22
  • Configuration Descriptor21:08
  • Interface Descriptor 022:35
  • Interface Descriptor 125:43
  • String Descriptors9:47
  • PIDs and bRequests24:09
  • Class Specific bRequests9:28
  • A simple FIFO36:16
  • Transmit FIFO Design 120:19
  • Transmit FIFO Design 239:31
  • Receive FIFO Design 14:59
  • Receive FIFO Design 25:42
  • Receive FIFO Design 319:44
  • USB Top Level Block Diagram4:45
  • Top Level Ports9:09
  • Top Level VHDL 111:12
  • Top Level VHDL 215:03
  • Top Level VHDL 314:21
  • Top Level VHDL 427:31
  • Central State Machine Flow Chart23:35
  • Central State Machine - Setting up the Framework32:20
  • Central State Machine - Control Transfers 121:09
  • Central State Machine - Control Transfers 219:20
  • Central State Machine - Control Transfers 319:54
  • Central State Machine - Data PID Toggle Process17:56
  • Central State Machine - Decode INOUT Requests11:50
  • Central State Machine - Get Line Coding23:18
  • Central State Machine - Simple Get Requests5:51
  • Central State Machine - Get Descriptor Request 119:07
  • Central State Machine - Get Descriptor Request 220:43
  • Central State Machine - Get Descriptor Request 332:46
  • Central State Machine - Set Line Coding10:01
  • Central State Machine - Decode PID12:34
  • FIFO Instantiation15:14
  • Central State Machine - Bulk Data Handling25:51
  • Central State Machine - Consolidation16:58
  • Completing USB Top Level Module21:19
  • Making Final Tweaks34:07
  • Adding Some Useful Comments26:39
  • Top Level Test Bench - The Approach12:24
  • Top Level Test Bench 118:47
  • Top Level Test Bench 214:23
  • Top Level Test Bench 318:38
  • Top Level Test Bench 418:17
  • Top Level Test Bench 59:05
  • Top Level Test Bench 612:34
  • Test Case 1 - Set Address27:51
  • Test Case 2 - Get Descriptor33:17
  • Test Case 3 - Host Writes Data14:36
  • Test Case 4 - Host Reads Data13:34
  • Hardware Test Model7:25
  • Hardware Test Fixture31:55
  • The Quartus Project26:45
  • Pin Assignments and Binary Files20:02
  • Hardware Functional Testing15:00
  • Debugging With Signal Tap32:25
  • Conclusion1:49

Requirements

  • Must have a basic understanding of the VHDL language
  • Understanding clocks, resets, and synchronous logic
  • Able to design simple finite state machines
  • If you have completed an introductory VHDL course, you are well prepared for this material.

Description

Add USB connectivity to your FPGA project

USB is everywhere — from keyboards to mice to embedded devices and development tools to production hardware. Yet in many FPGA projects, USB is treated as a black box, hidden behind prebuilt IP cores or software libraries.

In this course, you’ll do something different: you’ll build a working USB CDC (virtual COM port) interface entirely in VHDL, gaining a deep, practical understanding of how USB works at the hardware level — not just how to use it.


Who This Course Is For

This course is designed for engineers, students, and hobbyists who already have a basic understanding of VHDL and want to move beyond simple demonstration projects.

It’s ideal if you:

  • Understand basic VHDL concepts such as signals, processes, and state machines

  • Want to learn how real communication interfaces are implemented in hardware

  • Are curious about how USB works beyond libraries and vendor IP cores

  • Want to design FPGA systems that interact directly with a PC

  • Are comfortable working at the register, protocol, and timing level

This course focuses on understanding and building a USB CDC interface from first principles, not on using prebuilt blocks or high-level abstractions.

Not for you if:

  • You are completely new to VHDL or digital design

  • You are looking for a plug-and-play USB solution

  • You only want to use vendor-provided USB IP cores

  • You expect minimal HDL code or a purely software-driven approach

What You Will Learn

By the end of this course, you will be able to:

  • Understand USB architecture at the hardware and protocol level

  • Implement a USB CDC interface entirely in VHDL

  • Create and manage USB descriptors and handle enumeration

  • Design bulk IN and OUT endpoints for data transfer

  • Build FIFO-based data paths between USB endpoints and FPGA logic

  • Debug USB communication using simulation and real hardware

Why This Course Is Different

Many USB tutorials rely on vendor IP cores or software stacks — this course does not.

Instead, you’ll:

  • Build everything in VHDL from the ground up

  • Understand what each block does and why it exists

  • Learn to debug protocol-level issues

  • Take away knowledge you can reuse on other projects or platforms

The goal isn’t just to make something work — it’s to understand why it works.


Practical Outcomes

You won’t just learn theory. You will:

  • Build a working USB CDC device in VHDL that appears as a virtual COM port on a PC

  • Exchange data between a PC and FPGA using TX and RX FIFOs

  • Develop a solid understanding of USB device architecture

  • Gain a reusable USB foundation adaptable to other device classes or custom protocols

  • Prepare for more advanced FPGA and embedded projects

Skills You’ll Take Away

After completing this course, you’ll have:

  • A deep understanding of USB devices at the protocol level

  • Practical experience designing medium-sized VHDL systems

  • A solid foundation for advanced topics such as Ethernet, ADC/DAC interfacing, and system-level FPGA design

Recommended Background

Before starting this course, you should be comfortable with:

  • Writing and simulating simple VHDL modules

  • Designing simple finite state machines

  • Understanding clocks, resets, and synchronous logic

  • Using an FPGA toolchain to build and program a design

If you’ve completed an introductory VHDL course, you are well prepared for this material.


Hardware Platform (FPGA Explorer Board)

This course uses a modern FPGA development platform based on a Cyclone 10 LP device, featuring USB, SDRAM, user I/O, and other peripherals suitable for real-world projects.

All lessons, examples, and exercises have been tested on this platform, letting you follow along step by step without needing additional hardware. Focus stays on learning VHDL and system design, not on hardware workarounds.

This same platform will be used in future courses covering:

  • Ethernet communication

  • ADC and DAC interfacing

  • Advanced FPGA system design

Search eBay for "FPGA Explorer Board". See "FPGA_Explorer_Board.pdf" for more details.

Search eBay for "Byte Blaster Programmer". - You will need this to program the FPGA.


Ready to move beyond basic VHDL and start building real interfaces?

Join the course and take the next step in your FPGA journey.

Who this course is for:

  • Students with basic VHDL knowledge looking to move beyond simple demos
  • Hobbyists and makers interested in USB-enabled FPGA projects
  • Engineers or embedded developers who want hands-on FPGA experience
  • Anyone curious about USB device protocols and low-level FPGA design
  • Learners who want to build reusable skills for advanced FPGA projects

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