UPF Power Aware Design & Verification

Navigate the VLSI design phases from market analysis and product specifications to fabrication, highlighting design spaces, architectures and verification, and power-aware techniques to reduce dynamic power.

Contrast RTL behavioral modeling with power aware UPF verification to show how unconnected power rails, voltages off, isolation cells, and level shifters affect determinism.

Explore UPF basics, including power intent, power domains, power supply networks, isolation cells, level shifting, retention strategies, and verification approaches for design implementation.

Explore power domains in design verification by creating domains, including scope, and assigning CPU, video, and modules like B1, B2, and B3 to distinct domains.

Master power supply networks by learning about supply nets and supply ports. Create supply nets for a power domain, assign port directions, and connect nets with resolution and reuse.

Use supply side to define abstract supply sets and power domains, enabling reusable upf designs with simple isolation and retention strategies.

Explore how power switches control gated power domains by using enable signals from a PMU/BMC to turn input supply into output supply, detailing on/off states and power gate behavior.

This lecture explains building a four-state power state table for CPU, video, and display power domains in UPF, defining supply ports, power nets, and valid on/off combinations to drive verification.

Explore how level shifters translate signals between voltage domains to preserve logic values, enabling upshifting and downshifting across CPU to video boundaries, with configurable location.

Learn how isolation cells act as buffers between power domains, enforcing predetermined output values, with isolation enable logic, power-supply requirements, and policy-based application to signals.

Explore input and output isolation cells in power-aware design, comparing domain-specific isolation, power nets, and isolation policies to securely control signals across CPU and video domains.

Learn how retention cells preserve state across power off via always alive and shadow register schemes, enabling restoration on power up and balancing power, area, and performance trade-offs.

Learn the differences between flat and hierarchical UPF design, creating all power domains in one flat scope versus decomposing into CPU and video hierarchies with scoped components.

Trace the UPF evolution from 1.0 to 3.0, noting new commands, power modeling constructs, and deprecations. Explore the move to information modeling databases enabling object-based power aware design and verification.

Explore popular power saving techniques for UPF design and verification, including clock gating, power gating, dynamic voltage and frequency scaling, and multi-voltage domains to reduce dynamic and static power.

Identify and verify the design using static verification to catch syntax, semantics, structural and consistency issues in power domains and isolation cells before performing costly dynamic verification.

learn dynamic verification for power aware design by modeling top-level power rails, using UPF to control power supplies, and testing power-on sequencing through test benches or UPF-driven switches.

Explore dynamic verification with simstate modelling, introducing same state for power domains, comparing 1.0 and 2.0 standards, and detailing normal, corrupt, and corrupt activity states.

Explore low power coverage in dynamic verification, covering power domains, supply networks, isolation and retention, and how coverage reports reveal on/off transitions and state combinations.

Explore low power assertions in both inbuilt simulator properties and user defined checks. Verify power sequences, isolation behavior, and guard conditions to boost confidence in low-power design.

Explore instrumentation versus instantiation in power aware design and verification, comparing in-design isolation and retention cells with UPF-based isolation, and understanding how power components are instantiated or instrumented.

Explore hard macros as pre-implemented blocks used for verification and implementation, and liberty files offering partial power architecture details with upf-style interface properties like power and ground pins.