
Contrast RTL behavioral modeling with power aware UPF verification to show how unconnected power rails, voltages off, isolation cells, and level shifters affect determinism.
Learn how retention cells preserve state across power off via always alive and shadow register schemes, enabling restoration on power up and balancing power, area, and performance trade-offs.
Explore low power coverage in dynamic verification, covering power domains, supply networks, isolation and retention, and how coverage reports reveal on/off transitions and state combinations.
Exhaustive course spanning across 6+ hours of on-demand video lectures.
Comprises of 4 major sub-sections:
Need of UPF and UPF Basics (~1 hour 1 min)
+ VLSI Design Phases
+ RTL Simulation Vs Power Aware UPF Simulation
+ UPF Basics
UPF Power Aware Design (~2 hours 51 mins)
+ Power Domains
+ Supply Nets/Ports – Power Supply Network
+ Supply Sets – Power Supply Network
+ Power Switches
+ Power State Table
+ Level Shifters
+ Isolation Cells
+ Input Vs Output Isolation Cells
+ Retention Cells
+ Flat UPF Vs Hierarchical UPF
+ UPF Evolution 1.0 Vs 2.0 Vs 2.1 Vs 3.0
UPF Power Aware Verification (~2 hours 4 mins)
+ Popular Power Saving Techniques
+ Static Verification
+ Dynamic Verification 1 – Controlling Power Supplies
+ Dynamic Verification 2 – Simstate Modelling
+ Dynamic Verification 3 – Power Coverage
+ Dynamic Verification 4 – Low Power Assertions
Miscellaneous Concepts (~11* mins)
+ Instrumentation Vs Instantiation
+ Hard Macros and Liberty Files
* New lectures might be added based upon popular user feedback and request.