
Explore the metal-oxide-semiconductor capacitor, a three-layer structure that behaves like a parallel-plate capacitor, with area-based capacitance given by permittivity over distance under applied voltage.
Explore how negative bias on a metal contact drives hole accumulation at the semiconductor surface, bending energy band structure and forming a charge distribution at the metal insulator semiconductor interface.
Examine surface potential, its link to equilibrium and intrinsic Fermi levels, and the onset of strong inversion, while connecting electrostatic potential to electron and hole concentrations.
Describe the onset of strong inversion as the inversion-layer carrier concentration reaching the substrate's majority carrier concentration, with band bending and increased electron density in the inversion layer.
Analyze ideal MOS curves by linking constant oxide-field and linearly varying semiconductor field to oxide and surface potentials, noting inversion-layer charge and the resulting linear-to-parabolic potential profile.
Compute the maximum depletion width wmax in silicon by relating surface potential, acceptor and intrinsic concentrations, and permittivity, then evaluate with the given values to obtain wmax ≈ 1.4×10^-5 cm.
Explore non-ideal conditions in a MOS capacitor, including non-zero work function difference and oxide interface effects, and the resulting internal fields, Fermi level alignment, depletion, toward flat-band.
Compute the metal-semiconductor work function difference under non-ideal conditions using modified work function and modified electron affinity with silicon doping data. Derive the barrier potential at the metal-semiconductor interface.
Explore induced and implanted channels in mosfets, contrast enhancement and depletion modes, and explain inversion layers, mos capacitor behavior, and the role of gate and threshold voltages in the channel.
Explore how depletion and enhancement MOSFETs differ in drain current and channel formation, and define threshold voltage as the minimum gate bias to establish or disable conduction.
Explore the three-dimensional mosfet structure on a silicon substrate, contrasted with its two-dimensional representation, and highlight channel length, oxide thickness, and gate material options like metal, aluminium, or polysilicon.
Explain p-mosfet characteristics in enhancement and depletion modes, including negative threshold voltages and the onset of drain current, with three-terminal representations, saturation and linear regions.
Derive the MOSFET current equation in saturation and linear regions, linking drain current to W/L, mobility, oxide capacitance, and gate voltage through inversion layer concepts.
Explore threshold tailoring via shallow boron implantation beneath the oxide to form a negative charge sheet that shifts the MOSFET threshold voltage toward a positive value.
Understand the body bias effect, or substrate bias, and how bulk potential VB modifies the depletion region between source and bulk, shifting the threshold voltage.
This lecture introduces the bipolar junction transistor, its three-terminal two-junction structure with emitter, base, and collector, and explains the emitter-base and base-collector junctions, current directions, and common configurations.
Explore the basic operation of a bipolar junction transistor, including forward bias of the emitter-base junction, minority-carrier injection, and their sweep into the collector under reverse saturation.
Explore the common-base current gain in a BJT, defined by the transport factor alpha. Relate collector current to emitter and base currents via alpha and gamma.
Revisit emitter efficiency gamma by defining it as the ratio of emitter injection current to total emitter current, and show how base and emitter doping affect gamma.
Explore how minority carrier concentrations vary exponentially near a p-n junction under forward and reverse bias, with carrier injection, diffusion in the neutral base, and saturation effects.
this lecture presents the Ebers-Moll model of a bipolar transistor as two back-to-back diodes, linking emitter and collector currents via alpha factors and junction interaction.
Explore how the input characteristics of a common emitter transistor shift with collector voltage due to the Early effect, illustrating input curves, forward bias, and base-emitter behavior.
Explore the avalanche multiplication and breakdown mechanisms in bipolar transistors, including base-open and emitter-open configurations, and derive the current gain m = 1/(1−α) under breakdown conditions.
Analyze how a bipolar transistor's neutral base governs injected minority-carrier electrons and diffusion. Use maximum electron concentration and diffusion coefficient to estimate diffusion current density, noting linear approximation is invalid.
This is an undergraduate course on semiconductor device physics. This course is the second part in a series of two courses on semiconductor device physics.
For any electronics student understanding transport phenomena of charge carriers, drift current, diffusion current, energy band theory of semiconductors, electron hole pairs(EHPs), Junction formation in a diode, extending the device physics to three terminal devices like BJT and MOSFET is necessary.
My previous course "undergraduate course on semiconductor device physics-I" is a prerequisite for complete understanding of this course.
Metal-Oxide-Semiconductor combination forms a capacitor and that capacitive action is to be understood well in terms of threshold voltage, CV characteristics. Though our major focus is on ideal MOS capacitor, non-idealities are also discussed up to some extent.
Based on the knowledge of MOS capacitor, if we look at the transport of charge carriers in a three terminal device MOSFET it gives a complete picture of all MOSFET transistor structures namely, enhancement MOSFET & depletion MOSFET in both p-type and n-type substrates. A MOSFET is explained up to threshold control.
Another transistor is Bipolar junction transistor(BJT). BJT characteristics and device parameters are explained with respect to input and output characteristics.
About Author:
Mr. Udaya Bhaskar is an undergraduate university level faculty and GATE teaching faculty with more than 15 years of teaching experience. His areas of interest are semiconductors, electronic devices, signal processing, digital design and other fundamental subjects of electronics. He trained thousands of students for GATE and ESE examinations.