
What is coverage and need of coverage
Code coverage and Functional coverage
Covergroups and Coverpoints
Coverpoint bins
Example
Assertions
Need for Assertions
Types of assertions
What is TLM
Advantages of TLM
Ports in TLM
Explore transaction level modeling as abstracting inter-component communication. Define TLM interfaces with methods and protocols to enable modular, plug-and-play design, fast simulations, reference models, and performance analysis.
Learn how analysis ports in tlm enable non-intrusive observation of transactions by broadcasting data to multiple analysis exports, such as scoreboards and monitors, via a void write method.
Explore the Ahb protocol from the Amba family, enabling high bandwidth, low latency master-slave communication with burst transfers, single clock operation, and configurable bus width.
Explore how the AHB bus uses a centralized arbiter to grant bus access. Learn the address and data phases and how pipelining enables higher throughput with ready and slave responses.
Demonstrate ahb lite simple transfer, where the master drives address and control signals, the slave samples them, and the master receives data or a status response across three clocked cycles.
Analyze how wait states affect AHB transfers between master and slave, from zero wait states to one wait state, and how delayed data phases ripple through subsequent address transfers.
Automate verification with UVM to boost efficiency and quality through coverage driven environments, automated stimulus with constraint randomization, checking using monitors and scoreboards, and tracking code, functional, and assertion coverage.
Explore the UVM environment setup, including the configuration database, configuration mechanism, UVM factory, and UVM package, to flexibly configure testbenches at runtime.
Explore the UVM phases—build, connect, run, and cleanup—and how top-down build creates a modular test bench, bottom-up connect finalizes connections, run drives stimuli, and cleanup covers extract and report.
Explore the UVM testbench architecture, a modular, reusable environment built from UVM components, with agents, sequencers, drivers, monitors, and scoreboards that verify the design under test and enable horizontal reuse.
Extend the UVM sequence class to create user defined sequences that generate, control, and manage parameterized transactions using request and response handles to drive the driver.
Explore the UVM create macro in UVM for dynamic creation of sequence items or sequences via the UVM factory, with factory overrides ensuring correct types.
Use the uvm_do_pri_with macro to create, randomize, and send a sequence item or sequence with priority-based execution and inline constraints.
Explore UVM do macro interaction in a UVM testbench, detailing sequence, sequencer, and driver coordination through create, start item request, get next item request, randomize, finish item, and item done.
Get a high level overview of the UVM testbench top, including environment with scoreboard and agent, and interface, clock, reset generation, config db, and wave dumping.
Synchronize the driver sequencer handshake to flow transactions in a UVM testbench by transferring TX data to the duty via the sequence item port and signaling item done.
Learn how UVM sequencer arbitration decides which sequence sends data when multiple sequences contend, using priorities, fairness, and optional custom rules.
Mastering UVM for ASIC/SoC Verification with QuantSemicon: From Fundamentals to Industrial Applications
Are you ready to unlock the full potential of the Universal Verification Methodology (UVM) and elevate your design verification skills to an industrial level? This comprehensive course, developed by QuantSemicon’s expert team, is designed for both beginners and advanced learners who want to master UVM for ASIC/SoC verification. With a hands-on approach and real-world examples, this course will take you from the fundamentals of UVM to advanced methodologies, preparing you for the challenges of the semiconductor industry.
What You’ll Learn:
UVM Basics: Begin your UVM journey by understanding the core components and architecture. Learn about UVM testbenches, agents, sequences, and how UVM standardizes verification environments across projects for scalability and reusability.
UVM Testbench Architecture: Understand how UVM organizes a verification environment with components like the driver, monitor, and scoreboard. Learn to build modular and reusable testbenches that improve efficiency in verification.
Hands-On Industrial Examples: Gain practical experience with real-world projects. This course provides detailed examples such as verification environments for protocols like the Advanced Peripheral Bus (APB), preparing you to handle industrial-scale UVM projects. You will also explore in-depth verification scenarios for AHB, AXI, and RISC-V in future modules.
Transaction-Level Modeling (TLM) in UVM: Learn how TLM simplifies communication between components, allowing you to build flexible, scalable verification architectures that are used in complex SoC and ASIC projects.
Quizzes & Assessments: Each module includes quizzes to ensure you’ve absorbed the material and are ready to move to the next level. These interactive assessments are designed to solidify your knowledge and keep you on track.
Advanced UVM Features: As you progress, dive deeper into advanced UVM features like the UVM Register Abstraction Layer (RAL), UVM factory, virtual sequences, and configuration management, preparing you for complex verification challenges.
SystemVerilog Integration: Throughout the course, you’ll learn how UVM integrates seamlessly with SystemVerilog, leveraging its object-oriented programming features, assertions, and randomization techniques to create powerful and efficient testbenches.
Course Highlights:
Comprehensive UVM Coverage: From basic to advanced UVM concepts, including transaction-level modeling, agents, sequences, and more.
Real-World Examples: Every concept is reinforced with industrial examples, giving you confidence to apply UVM to real-world projects.
Modular and Reusable Testbenches: Learn to create scalable verification environments for complex designs.
Interactive Quizzes & Assessments: Test your understanding with quizzes and exercises after each module.
Future-Ready Knowledge: Prepare for advanced UVM concepts such as UVM RAL and virtual sequences.
By the end of this course, you will have a robust understanding of UVM, hands-on experience building scalable testbenches, and the skills to tackle complex verification challenges in the industry.
Whether you are a student preparing for a career in the semiconductor industry or a professional looking to advance your verification skills, this course provides a structured path to mastering UVM. Join us and take the first step toward becoming a UVM expert!