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SystemVerilog/UVM for ASIC/SoC Verification Part 1
Rating: 4.4 out of 5(13 ratings)
63 students

SystemVerilog/UVM for ASIC/SoC Verification Part 1

Basic SystemVerilog/UVM Concepts Explained using AMBA APB Example
Created byQuant Semicon
Last updated 11/2024
English

What you'll learn

  • Learn the basics of SystemVerilog, different data types, procedural blocks, and control flow constructs.
  • Explore how OOP concepts facilitate reusable and scalable testbenches.
  • Learn how to use SystemVerilog interfaces to simplify connectivity between design modules.
  • Learn how to verify correct master-slave interaction and signal behavior in APB transactions.
  • Learn basics of UVM
  • System on Chip Design Verification Concepts

Course content

1 section • 20 lectures • 5h 23m total length

  • Introduction to Design Verification15:50

    • SoC (System on Chip)​

    • What is Verification​

    • Verification methodology

    • Verification flow

  • Introduction to SystemVerilog and Datatypes18:13

    • Overview of SystemVerilog​

    • Importance and applications in hardware design​

    • Basic syntax and structure​

    • Data types (integer, real, bit, logic, etc.)​

    • Variables and constants​

  • Arrays and Memories25:51

    • Array declaration and initialization​

    • Multi-dimensional arrays​

    • Memories and memory initialization​

    • Queues​

    • Strings​

  • Arrays & Memories: Array Manipulation Methods Part 13:42
  • Array & Memories: Array Manipulation Methods Part 25:02
  • Advanced Data Types13:35

    • Unsigned and Signed data types​

    • Unions​

    • Structures ​

    • Enumerated types​

    • Operators, expressions and control statements​

  • Classes and OOP Concepts43:37

    • ​Basic OOP Concepts​

    • SystemVerilog Classes​

    • Abstract class​

  • Randomization and Constraints​ Randomization28:31

    • ​Randomization​

    • Randomization Methods​

    • Constraints​

  • Task and Functions​26:13

    • ​Task & Functions​

    • Return Statement and Void Functions​

    • Function output arguments​

    • Passing arguments​

    • Default arguments​

  • Task & Functions: Pass by Reference3:37
  • Connectivity blocks in SV​32:28

    • ​Connectivity blocks​

    • Introduction to Synchronization​

    • Mailbox, Semaphore​

    • Event scheduling

  • Program Block​10:37

    • ​What is program block?​

    • Event Scheduler​

    • SystemVerilog Queue​

  • Inter process Communication​25:23

    • ​Thread and Virtual Interface​

    • Creating and Controlling thread​

    • Wait timer​

    • Passing interface instances ​

    • Parameterized class

  • SystemVerilog Testbench Architecture25:40

    • ​SystemVerilog Testbench​

    • Verification Plan​

    • Full adder design and Verification Approach​

    • Testbench Infrastructure​

  • Introduction to UVM​7:16

    • ​What is UVM?​

    • UVM Testbench Architecture​

    • Basic Components of UVM Testbench

  • Basics of APB Protocol9:28

    • ​Introduction to Protocol​

    • Introduction to APB Protocol​

    • Signal Descriptions​

    • Operations and Flow Control Mechanism

  • APB Testbench Project1:55
  • APB Testbench Explanation : Part 1 (Design)7:17
  • APB Testbench Explanation : Part 29:58
  • APB Testbench Explanation : Part 38:58

Requirements

  • Digital Design
  • Logic Design flow
  • Verilog
  • Digital Electronics
  • Basic programming Knowledge

Description

Mastering SystemVerilog/UVM for ASIC/SoC Verification with Quant Semicon: From Basics to Industrial Applications

Are you ready to dive deep into the world of SystemVerilog and unlock its potential for industrial-level design and verification? Our comprehensive course specifically designed by Quant Semicon's Team is for both beginners and advanced learners who want to master SystemVerilog (SV) and its object-oriented programming (OOP) concepts. With a hands-on approach and real-world examples, this course will take you from the basics of SV to advanced applications, preparing you for the challenges of the semiconductor industry.

What You’ll Learn:

  1. SystemVerilog Basics: Start your journey by understanding the core features of SystemVerilog. We’ll cover syntax, data types, control structures, and how SV enhances traditional Verilog for modern design and verification needs.

  2. Object-Oriented Programming (OOP) in SV: Discover how OOP principles such as inheritance, encapsulation, and polymorphism are applied within SV. Learn why these concepts are crucial for creating scalable, maintainable verification environments.

  3. Hands-On Industrial Examples: Theory alone isn’t enough—this course is packed with real-life examples. We’ll guide you through implementing practical, industry-relevant examples like the Advanced Peripheral Bus (APB), giving you the confidence to handle real projects. In coming levels we will also be learning Protocols like AHB, AXI, low peripheral communication and also expand our knowledge on RISC V.

  4. Quizzes & Assessments: Each module includes quizzes designed to test your knowledge and ensure you’re ready for the next level. These interactive assessments help you retain what you’ve learned while keeping you engaged.

  5. Advanced SystemVerilog Concepts: As you progress, we’ll delve into advanced features such as assertions, coverage, and randomization, preparing you for the complexities of large-scale designs.

  6. UVM Introduction: The course also provides a solid introduction to the Universal Verification Methodology (UVM). You’ll grasp the basics of UVM and understand how it integrates with SystemVerilog, setting the stage for mastering UVM in future projects.

Course Highlights:

  • Engaging, Real-World Examples: Every concept is backed by practical, real-life scenarios.

  • Detailed OOPs Coverage: Master OOPs, the cornerstone of efficient SV programming.

  • Quizzes & Practice Exercises: Test your knowledge and apply what you’ve learned.

  • UVM Foundations: Prepare for advanced UVM concepts in Part 2 of the course.

By the end of this course, you will have a strong foundation in VLSI verification principles and hands-on experience, preparing you to tackle complex verification challenges in the industry.

Whether you’re a student preparing for a career in the semiconductor industry or a professional looking to sharpen your skills, this course provides a complete, structured path to mastering SystemVerilog. Join us and take the first step toward becoming a SystemVerilog expert!

Who this course is for:

  • Students: Electronics, Microelectronics, VLSI, Embedded
  • Working Professionals : VLSI design professional, Verification Engineers, Verification Leads

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