SoC Design 3: A Professional Systemverilog Code walk-through
3.8 (73 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
1,410 students enrolled

SoC Design 3: A Professional Systemverilog Code walk-through

VLSI : Learn Verilog / System Verilog for SOC Design - Get exposed to a complete, industry standard project in detail
3.8 (73 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
1,410 students enrolled
Created by Ajith Jose
Last updated 5/2019
English
Current price: $41.99 Original price: $59.99 Discount: 30% off
5 hours left at this price!
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This course includes
  • 2.5 hours on-demand video
  • 1 article
  • 4 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Write SystemVerilog SoC design code in a professional way
Requirements
  • This course is a practical session explaining how to a complete SoC design in SystemVerilig and this is not explaining the theory. Thus you need to have the basic knowledge of SystemVerilog Design coding
  • Also you need to have the basic knowledge about Digital Circuits.
Description

SystemVerilog course teaches the concepts of SoC/IC design and it is more of a practical session walk-through. Here, a professional SoC design code is explained in detail. This will enable the student to get exposed to an industry standard SoC code and the techniques behind writing it.

This course is started by explaining the interface feature in SystemVerilog. It explains the usage of interface and few language features like enumeration and macros which are used in the coding example. Next, the process of developing general SV components is explained with examples. Finally, a complete design code of a simple SoC is explained with minute details.

 By taking this course, you will be more confident in writing SV design code as you are learning  the process of developing standard SoC designs. This will be an excellent platform to master design coding styles in SystemVerilog.

Who this course is for:
  • Students with basic SV design coding knowledge who wants to get exposed to an industry standard SoC design coding project
Course content
Expand all 26 lectures 02:29:28
+ Enumeration and Compiler directives
2 lectures 06:23
Enumeration & User Defined datatype
04:10
Compiler Directives
02:13
+ General Components
5 lectures 27:56
General Components 1
05:11
General Components 2
03:44
General Macros
04:17
Writing a FIFO
05:17
FIFO Controls
09:27
+ DUT Design Description
3 lectures 16:19
AXI and OCP Protocol Description
05:20
DUT Description
04:09
AXI-OCP Converter
06:50
+ Code Walk-through : AXI -OCP Conversion
6 lectures 53:27
AXI Front End Design
03:40
General Components Code
04:15
AXI Write Front End Code
14:26
AXI Read Front End Code
03:10
AXI-OCP Converter - State Machine
14:57
AXI-OCP Converter Code
12:59
+ Code Walk-through : OCP-AXI Conversion
5 lectures 28:30
OCP Read Return Front End
06:55
OCP-AXI Converter
08:39
Interconnect Code
04:15
Simulation
06:13
Concluding Coding
02:28
+ Summary
3 lectures 06:56
Summary
01:26
Bonus Lecture
00:33