This Systemverilog course teaches the System-On-Chip design verification used in VLSI industry. It is teaching only a specific topic in SV, the simulation time regions.
While learning SV verification or even after spending years in writing test-benches, it is a hard task for most of the verification engineers to answer anything demanding in depth knowledge in simulation time regions. Here in this course, this problem is addressed in a simplified manner by explaining every time regions in detail, and connecting different code regions to time regions. You will going through following lectures in this course.
Components of a generic SV design/TB code
Introduction to Simulation Regions
Active, Reactive, NBA Regions
Re-Active, Re-Reactive, Re-NBA Regions
Class & Functional Coverage Execution Regions
As example explaining advancing simulation through different regions for each time-slot
By taking this course, you will be able to explain what is happening in simulation in each time slot with respect to the code you write. This would be an excellent platform to brush up your SV skills and to address common verification questions confidently.
Who this course is for:
Anyone who does coding in Systemverilog, but have no clear idea about time regions specified in LRM.
A post graduate in electronics engineering with over 12+ years of experience in ASIC design & verification with major semiconductor companies like Intel India and ARM UK. Expert in Systemverilog for design & verification coding, and Universal Verification Methodology (UVM) . Passionate about teaching.