Systemverilog Verification -6: Simulation Regions in Detail
4.0 (15 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
602 students enrolled

Systemverilog Verification -6: Simulation Regions in Detail

VLSI: Simulation Time regions in Systemverilog - Uncovering mystery behind the scenes in an SV simulation.
4.0 (15 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
602 students enrolled
Created by Ajith Jose
Last updated 5/2019
English
Current price: $34.99 Original price: $49.99 Discount: 30% off
5 hours left at this price!
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This course includes
  • 1.5 hours on-demand video
  • 1 article
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Simulation Time regions in Systemverilog
Requirements
  • Be familiar with basics Systemverilog coding
Description

This Systemverilog course teaches the System-On-Chip design verification used in VLSI industry. It is teaching only a specific topic in SV, the simulation time regions.

While learning SV verification or even after spending years in writing test-benches, it is a hard task for most of the verification engineers to answer anything demanding in depth knowledge in simulation time regions.  Here in this course, this problem is addressed in a simplified manner by explaining every time regions in detail, and connecting different code regions to time regions. You will going through following lectures in this course.

  • Components of a generic SV design/TB code

  • Introduction to Simulation Regions

  • Preponed Region

  • Active, Reactive, NBA Regions

  • Observed Regions

  • Re-Active, Re-Reactive, Re-NBA Regions

  • Postponed Region

  • Class & Functional Coverage Execution Regions

  • As example explaining advancing simulation through different regions for each time-slot

By taking this course, you will be able to explain what is happening in simulation in each time slot with respect to the code you write. This would be an excellent platform to brush up your SV skills and to address common verification questions confidently.

Who this course is for:
  • Anyone who does coding in Systemverilog, but have no clear idea about time regions specified in LRM.