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Introduction to SystemVerilog Functional Coverage Language
Rating: 4.5 out of 5(231 ratings)
4,296 students

Introduction to SystemVerilog Functional Coverage Language

Introductory Step-by-step overview of SystemVerilog Functional Coverage features, methodology/apps FROM SCRATCH
Created byAshok B. Mehta
Last updated 2/2025
English

What you'll learn

  • Get you up and running in the shortest possible time. No knowledge of SystemVerilog OOP or UVM required
  • Make you confident in seeing that you have fully 'functionally' covered your design and testbench before tape-out
  • Make you knowledgeable in one of the most important and critical part of overall Design Verification landscape
  • Will make your resume even stronger in the competitive DV landscape.

Course content

4 sections • 14 lectures • 2h 59m total length

  • Introduction6:37

    This lecture will establish the role of Functional Coverage under the IEEE-1800 SystemVerilog umbrella. It will also highlight the difference between code coverage and functional coverage.

  • Functional Coverage: Methodology15:00

    This lecture will show you the Functional Coverage Methodology which encompasses, SystemVerilog Assertions (SVA) 'cover' + SystemVerilog Functional Coverage + Code Coverage. It also shows you how you can automate Test => Simulation => Coverage Evaluation => Test enhancement loop to reach a 100% coverage goal.

Requirements

  • This course will go step-by-step through each of Functional Coverage (FC) language feature and methodology component with practical applications at each step - FROM SCRATCH
  • You only need very basic knowledge of hardware design and verification
  • You do NOT need knowledge of Object Oriented Programming (OOP) or Universal Verification Methodology (UVM)

Description

The knowledge gained from this course will help you cover those critical and hard to find design bugs. SystemVerilog Functional Coverage Language and Methodology is a very important part of overall functional verification methodology and all verification engineers need this knowledge to be successful. The knowledge of FC will indeed be a highlight of your resume when seeking a challenging job or project The course offers step-by-step guide to learning of FC with real life applications to help you solidify your concepts and apply FC to your project in shortest possible time. FC helps the critical part of Functional/Temporal domain coverage which is simply not possible with code coverage.The course does not require any prior knowledge of SystemVerilog or OOP (Object oriented programming) or UVM. The course has 9 lectures that will take you step by step through FC language from scratch.

Who this course is for:

  • Hardware design and verification engineers, Verification IP developers and EDA application engineers are best suited for this course.
  • New college graduates will also benefit tremendously from this course.

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