SystemVerilog Functional Coverage for Newbie
What you'll learn
- Usage of Functional Coverage in Verification
- Implicit and Explicit Bins, Default bins
- Illegal bins, Ignore bins, WIldcard bins Default bins
- Covergroup, Sampling events, Reusable Covergroup
- Transition bins and Cross Coverage
- Usage of Functional Coverage in Verilog and SystemVerilog TB
- Demonstrations of Functional Coverage with Counters, Priority Encoders, Adders, FIFO, SPI and few other RTL's
Requirements
- Fundamentals of Verilog
Description
The verification process is becoming complex and time-consuming day by day with advances in the Hardware Description Languages and IPs. HDL has added capabilities that allow the engineer to Design and write Testbench for complex systems. But verifying designer intent and deciding set of right stimuli to meet the Verification plan is not always easy with HDL. Hence System Verilog introduces assertions and Coverage to fulfill this requirement by adding independent constructs to language. SystemVerilog assertions allow us to verify Designer intent in both Temporal and Non-Temporal domains. Functional Coverage act like feedback for the stimulus we are sending to DUT so that we could reach to best stimulus for verifying the plan in the least amount of time.
This course covers the fundamentals of different types of bins viz, Implicit bins, Explicit bins, Wildcard bins, Ignore bins, default bins, illegal bins with a demonstration of each of them in RTL. Fundamentals of Cover group, Reusable Covergroup, and different Sampling methods viz. event, sample() method, and User-defined Sample Method are discussed in detail. Functional Coverage gives us the ability to verify the relation between the signal by using Cross Coverage and detailed discussion on Cross coverage with different combination filtering strategies are covered in detail. Finally, Transition bins provide temporal abilities to Functional Coverage is also discussed in detail with projects demonstrating the usage of Functional Coverage in Verilog and SystemVerilog Testbench.
Who this course is for:
- Anyone interested in adopting Functional Coverage in the Verification process to generate Stimulus meeting Verification plans
Instructor
- 4.5 Instructor Rating
- 5,826 Reviews
- 19,295 Students
- 24 Courses
I currently serve as an instructor, where my responsibilities involve creating educational content for both undergraduate and postgraduate students. This content is designed to help them grasp the latest trends in VLSI (Very-Large-Scale Integration) technology. Prior to this role, I held the position of FPGA Developer Lead at one of India's premier Financial Technology companies. There, I led a team in the development of a cutting-edge High-Frequency Trading platform, leveraging Xilinx Alveo FPGA Cards.
Before my venture into the fintech industry, I dedicated three years as a VLSI Trainer at Mumbai University, India. Additionally, I spent one year as a Research Scientist at a renowned R&D center focused on Applied Electronic Research in India. During this time, I made significant contributions to projects such as the development of a Gradient Controller and a 64 MHz Receiver on FPGA for an indigenous MRI machine.
In my leisure hours, I have a passion for creating Udemy courses, and I have also collaborated with organizations like Larsen & Toubro Technology Services and Power International. In these collaborations, I played a pivotal role in designing various FPGA-based systems, including Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS (Data Transmission Systems). My primary areas of expertise and interest revolve around Front End VLSI Design, System-on-Chip (SoC) development, and Chip Verification.