Verification Series Part 2: Hands-On SystemVerilog Projects

Discover a 16-location, 8-bit fifo with first-in, first-out semantics, clocked write and read, empty and full flags, and a systemverilog verification interface.

Build a fifo verification environment with a transaction generator, driver, monitor, and scoreboard; use 8-bit data, random 50/50 write/read operations, and a queue-based golden data approach.

Verify a FIFO using a monitor, mailbox, and scoreboard; apply stimuli via a driver, collect responses, and ensure data matches between DUT and queue across write and read.

Design a Verilog SPI master verification environment that samples 12-bit data on new_data, drives chip_select, MOSI, and S_clock, and serially transmits 12 bits using an idle, enable, send, complete FSM.

Build a spi master verification environment using a randomized 12-bit d_in transaction with new_data and outputs, coordinating generator, driver, and scoreboard via mailboxes and events to validate data on mosi.

Verify spi master by collecting 12 MOSI bits into a 12-bit value and sending it via mailboxes to the scoreboard, then compare driver and monitor data for a data match.

Create an spi slave that reads 12 bits from MOSI on SCLK with chip select, converts to a 12-bit parallel word, and asserts done.

Build a verification environment for an spi module with master and slave. Use transactions with new_data, D_in, and D_out to drive, monitor, and check data matches on the scoreboard.

design a verilog uart verification environment with transmitter and receiver, using start bit, eight data bits lsb first, stop bit, no parity, and baud rate timing derived from a clock.

Develop a uart receiver with an independent clock generator, capturing eight lsb-first bits on rcs via a right-shift register and integrating a top module for transmitter and receiver verification.

Expose a transaction class-driven verification flow with an operation_type enum and rand/randc for write and read stimuli, using a driver, generator, and scoreboard to validate the dut.

Identify operation type from new_data and rx, collect serial data on the tx line into an 8-bit value, and compare uart p4 driver and monitor data in the scoreboard.

Verify uart p5 operations show reset done, read and write flows, data match across generator, driver, monitor, scoreboard mailbox for dut on rx and tx values 98 and 173.

explore i2c start and stop signaling in a hands-on ai device communication project, covering master-slave wake-up, address acknowledgment, and data transfer, with waveform timing and four-part bit duration.

Learn how I2C write and read transactions work, from start conditions and seven-bit addresses to msb-first data framing, the read/write bit, data bytes, acknowledge signals, and stop conditions.

Implement a SystemVerilog i2c master fsm that handles start, address, write/read operations with proper acknowledge, stop conditions, and open-drain signaling, using four-pulse bit timing.

Explore the i2c master design, including start and stop signaling, address and data framing, and ack handling. Understand bit timing with four-pulse subdivisions, sda scl control, and read/write semantics.

Explore the i2c slave memory that mirrors the master transaction, with 128 locations of 8-bit data addressed by a 7-bit address, initialized on reset, and supporting read/write operations.

Develop an I2C verification environment by building a testbench with a transaction class, random stimulus generator, and driver interactions to validate write and read operations.

Master I2C verification environment part 2 by monitoring the dut, validating memory writes and reads with a scoreboard and array, and logging data with proper timing and synchronization.

Explore building an I2C verification environment in SystemVerilog, wiring a driver and scoreboard to test fixed and randomized addresses and data, with write and read transactions and constraints.

Demonstrate APB signal interactions that drive memory read and write transactions, and use waveforms to verify APB memory through read/write cycles.

Learn APB transfer waveforms through write and read transactions with and without wait states, using select, enable, address, W data, and ready signals to verify a slave in SystemVerilog.

Explore APB read and write transactions, starting with a setup state using P select, PW data, address, and the operation, then enable signaling and RTL memory verification.

Design an APB slave with 32-bit address, 8-bit data, and 16-element memory; implement address, address value, and data value errors, and an idle/write/read state machine.

Build a SystemVerilog APB memory verification environment using a transaction with rand input ports, constraints, and a display method, coordinating generator, driver, monitor, and scoreboard.

Learn to model an axi-lite slave by implementing write and read channels (aw, w, b, ar, r) in a small memory, with an fsm-driven verification environment.

Implement a write path in a SystemVerilog FSM, sampling write addresses and data, updating a 128-entry memory, and issuing a write response or decode error with two-cycle memory fetch.

Capture an address when arvalid asserts, send acknowledgment, and verify the address is within 128. Provide data with rvalid after two fetch cycles if within 128; else decode error.

Apply random stimuli in a SystemVerilog testbench to verify write and read transactions on a DUT, including address five with café and out-of-range decode errors.

Design a SystemVerilog testbench for an AXI-Lite memory to generate stimuli for write and read transactions, using a transaction class and a generator, driver, monitor, scoreboard flow.

Construct a verification environment driver that applies generator stimuli through an interface, uses mailboxes for communication, and coordinates reset, write, and read transactions with a monitor and scoreboard.

Build a SystemVerilog verification environment with a monitor, scoreboard, and mailbox-driven driver to sample responses and validate write and read operations.

Designs a verification environment in SystemVerilog to test a restricted memory with write and read transactions, validating data integrity with a scoreboard, driver, and monitor.

Examine the ahb protocol by detailing signals like hclk, haddr, htrans, hwrite, hsize, hburst, hready, hresp, and hsel, and explain address and data phases plus response types okay and error.

Explore the ahb signal set in memory design, covering clock, write data, address, size, burst type, reset, s_select, and transfer type, with h_response, h_ready, and h_data outputs from the slave.

Understand burst modes in a memory design, including single transfers and incrementing bursts up to 1 kb, with h size selecting 1, 2, or 4 bytes per transfer.

Explore wrap and increment burst modes in SystemVerilog design, calculating boundaries and addresses for wrap 4/8/16 and increment 4/8/16 transfers, including edge burst, burst length, and size handling.

Understand the SystemVerilog fsm for a memory burst controller, covering reset decoder, address decode, length count, and burst modes including wrapping and increment.

Demonstrate read and write operations in a SystemVerilog memory controller, covering idle and check modes, address decoding, and burst transfers for single, unspecified length, wrap, and increment modes.

Build a SystemVerilog testbench by declaring an interface and transaction class to manage DUT signals. Use pseudo-random data, burst constraints, and a deep copy method to move transactions between components.

Use a generator class to create random values for rand-modified variables and send deep copies to the driver via mbx_GD, while mbx_GM communicates U data and length to the monitor.

Develop a class driver that accesses the hbor_if interface, uses a transaction tr and mailbox mbx_gd for burst-type design, and implements an active-low reset held for 10 clock ticks.

Drive memory transactions by applying burst-length four sequences from a generator to a dut, waiting for h-ready to complete each transfer and covering reads, writes, and burst patterns.

Understand a SystemVerilog driver that implements increment bursts of 4, 8, and 16 for write and read transfers, using random data, generator-supplied addresses, and a repeat-based sequence.

Explore the monitor class in SystemVerilog verification. Connect to a vif interface and mailboxes, sample address and data on ready edges, and send transactions to the scoreboard.

Explore building and verifying a scoreboard class for an AHB memory, with a 256-depth memory, 4-byte data, mailboxes, monitor, generator, driver, and testbench integration.

Verify burst mode by varying edge burst values, perform a single transfer with fixed address and length, write data 34 to address five, and verify reads match.

Verify burst modes by adjusting burst settings and observing reads and writes across four transfers, ensuring data matches at each address and handling default values and wrap and increment patterns.

Understand the wishbone protocol, its master and slave memory interface, and key signals like address, data, select, wstrobe, cycle, and ack for memory verification.

Explore a 256-depth memory interface in SystemVerilog, with 8-bit address/data, a strobe-driven FSM for read/write via a mode pin, two always blocks, and synchronous reset with ack.

Define the transaction class to model memory operations, declaring input and output ports, applying pseudo random constraints for write and read modes, and supporting deep copy and a debug printer.

Use the generator class to create transactions, send deep copies through a mailbox to the driver, and synchronize with driver and scoreboard via events after randomization and rate control.

Define a driver class for the WB interface, using a mailbox and transaction container to drive write, read, and random write tasks, including reset sequencing and handshake with acknowledgments.

Develop a monitor class to access an interface with a mailbox-based transaction, synchronize with clock edges, update and sample transaction data, and forward results to a school board for comparison.

Implement a scoreboard class that coordinates a mailbox and handles read and write transactions. It uses memory depth 256 and compares read data with expected values, displaying matches and mismatches.

The testbench top connects the interface, generates a clock, and merges events across generator, driver, and monitor to run ten random transactions and verify data matches.