SystemVerilog Assertions & Functional Coverage FROM SCRATCH

This lecture will introduce Immediate Assertions and Deferred Immediate Assertions

This lecture will discuss in-depth the definitions of sequence, property, assert and cover. It will also discuss Implication Operators such as Overlapping and Non-overlapping. This lecture is foundational to the course.

This lecture describes the phenomenon of vacuous pass with properties. What is it? And how do you solve this mystery?

This lecture will discuss how SystemVerilog Assertions are sampled in the pre-poned region of a clock edge. It will discuss nuances of singly clocked properties.

This lecture discusses the most fundamental semantic of the language - that being the concept of multi-threading and pipelined behavior. It then goes into the discussion of formal and actual arguments and their connectivity. other features discussed are assertion execution terminate system features such as 'disable iff'

SVA allows you to write properties / assertions for either VHDL or Verilog design. You write the assertions in SVA and 'bind' those to either VHDL or Verilog RTL.

This lecture discusses the so-called Sampled Value Functions, namely $rose and $fell

This lecture discusses Sampled Value Functions such as $past, $stable, $changed, $sampled, etc. It also discusses Global clocking PAST and FUTURE sampled value functions.

This lecture discusses fundamentals of Clock Delay and Clock Delay Range operators.

This lecture dives deep into the Consecutive Repetition Operator.

This lecture dives deep into Non-Consecutive repetition and Non-Consecutive GOTO operators. Shows the similarity and differences between the two operators

This lecture discusses the operators "throughout' and 'within'

This lecture discusses the operators 'and', 'or' and 'intersect' as applied to procedural code as well as concurrent assertion.

Continuing with previous lecture, this lecture further explores nuances of 'intersect' and 'or'

This lecture discusses the important concept of 'first_match' and its effective use in an Antecedent. It then follows with if-then-else, iff and 'implies' features

This lecture highlights the point that first_match makes most sense in using on the antecedent side.

$onehot, $onehot0, $isunknown, $countones

Assertion execution control tasks: $assertoff, $asserton, $assertkill, $assertpassoff, $assertpasson, $assertfailoff, $assertfailon, $assertnonvacuouson, $assertvacuousoff, $assertcontrol

This lecture continues with the previous lecture on multiple clocks

This lectures dives deep into SystemVerilog Assertions (SVA) 'Local Variables'. Plenty of applications are given.

SVA allows only constant delays in the ##[m] operator or ##[m:n] operator, where 'm' and 'n' are constants. This lecture shows you how to model a variable 'm' and 'n'.

Here we will address very fine detail on the pitfalls of incorrectly using local data assignment in 'and' and 'or' of sequences.

This lecture discusses 'expect', 'assume', Blocking 'action block' etc. important features of SVA.

This lecture shows how to write SVA assertion for an Asynchronous FIFO.

A few misc. topics, including effective use of 'attaching' (or calling) subroutines on the match of a sequence, use of sequence in Verilog procedural block sensitivity list or as an event trigger. Also, I am discussing how cyclic dependency work in SVA

In this lecture we will explore how recursive properties work and how to apply that in real life applications.

This lecture discusses the IEEE-1800 LRM 2009 and 2012 features such as 'let declarations' and 'checker'

In this lecture, we'll discuss some of the legal and illegal ways to assign variables; indexing loops, etc.

We will explore the concept of strong and weak properties. Also, we'll explore operators such as 'followed-by', 'always' and 'eventually'