SystemVerilog Assertions (SVA) for Newbie
What you'll learn
- Insights of System Verilog Assertions according to LRM 1800 2017
- Insights of Boolean, Sequence and Property Operators
- Power of the Concurrent and Immediate assertions
- Insights of System Tasks and Sampled Edge functions
- Usage of the Local Variables in Concurrent assertions
- Application of Immediate assertions to digital systems
- Application of Concurrent assertions to digital systems
- Application of the assertion in FSM
- Usage of the assertion in SystemVerilog TB
- Fundamental understanding of Verilog
Nowadays, Incorporating the Assertions in the Verification of the design is common to verify RTL behavior against the design specification. Independent of the Hardware Verification Language( HVL ) viz. Verilog, SystemVerilog, UVM used for performing verification of the RTL, the addition of the assertions inside the Verification code helps to quickly trace bugs. The primary advantage of using SV assertion over Verilog-based behavior check is a simplistic implementation of the complex sequence that can consume a good amount of time and effort in Verilog-based codes. SystemVerilog assertion has a limited set of operators so learning them is not difficult but choosing a specific operator to meet design specifications comes with years of experience. In this course, We will go through series of examples to build a foundation on choosing a correct assertion strategy to verify the RTL Behavior. The assertion comes in three flavors viz. Immediate Assertion, Deferred Immediate assertion, Final deferred immediate assertion, and Concurrent Assertion. An assertion is a code responsible for verifying the behavior of the design. Full Verification of the design essentially includes verification in Temporal as well as non-temporal domains. SV Immediate and Deferred assertions allow us to verify the functionality of the design in the Non-Temporal region and Concurrent assertion allows us to verify the design in the Temporal region.
Who this course is for:
- Anyone Interested in pursuing career in VLSI or RTL Verification domain
I currently serve as an instructor, where my responsibilities involve creating educational content for both undergraduate and postgraduate students. This content is designed to help them grasp the latest trends in VLSI (Very-Large-Scale Integration) technology. Prior to this role, I held the position of FPGA Developer Lead at one of India's premier Financial Technology companies. There, I led a team in the development of a cutting-edge High-Frequency Trading platform, leveraging Xilinx Alveo FPGA Cards.
Before my venture into the fintech industry, I dedicated three years as a VLSI Trainer at Mumbai University, India. Additionally, I spent one year as a Research Scientist at a renowned R&D center focused on Applied Electronic Research in India. During this time, I made significant contributions to projects such as the development of a Gradient Controller and a 64 MHz Receiver on FPGA for an indigenous MRI machine.
In my leisure hours, I have a passion for creating Udemy courses, and I have also collaborated with organizations like Larsen & Toubro Technology Services and Power International. In these collaborations, I played a pivotal role in designing various FPGA-based systems, including Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS (Data Transmission Systems). My primary areas of expertise and interest revolve around Front End VLSI Design, System-on-Chip (SoC) development, and Chip Verification.