Learn System Verilog for Verification

Topics Covered:

• Packed vs Unpacked Arrays – What’s the difference and why it matters

• Static Arrays – When your sizes are known and fixed

• Dynamic Arrays – Allocating memory at runtime

• Associative Arrays – Indexing with flexibility (integers, strings, enums!)

• Queues – Ordered collections with push/pop capabilities

By the end of this lecture, you will be able to:
-Choose the right array type based on your use-case
-Declare and manipulate different kinds of arrays confidently
-Use methods like push_back, pop_front, exists, delete, find_index with ease
-Write cleaner and more efficient SystemVerilog code for transaction modeling
-Handle variable-sized data structures in real-world testbenches (e.g., packet, scoreboard, mailbox)

At the end of lecture, Students would understand, SV classes concept, their object creation , default and custom constructor in system Verilog and automatic or static properties/methods in class.

At the end of lecture, students would understand how OOPS concepts (Inheritance, Polymorphism, Encapsulation, Abstraction) are applied using SV classes.

Event Regions in System Verilog: n this video, we understand Event Regions in SystemVerilog, a critical concept for anyone working in Design Verification (DV) using simulators like VCS, Questa, or XSIM. Here You’ll learn: What are simulation time slots and how events are scheduled. The purpose and execution order of Preponed, Active, Inactive, NBA, Observed, Re-active, and Postponed regions. Where $display, $monitor, blocking/non-blocking assignments, and assertions execute. Real coding examples to demonstrate how different assignments behave across simulation regions.

SystemVerilog Interfaces & Modports | Simplifying Connectivity in Testbenches In this video, we explore one of the most powerful features of SystemVerilog—Interfaces and Modports. These constructs help reduce port clutter and bring better structure, reusability, and direction control in testbench design. Topics Covered:

-What is an Interface in SystemVerilog?

-Why use Interfaces over traditional port connections?

-Syntax and real-world examples

-Role of Modports in controlling access directions

- Best practices in Design Verification testbenches

Whether you're a VLSI beginner, DV trainee, or preparing for SystemVerilog interviews, this video will help you build a strong foundation for writing clean and scalable testbenches.

Topics Covered:

• What is a clocking block and why it's needed

• Clocking block syntax and how to define input, output, and inout

• Clocking skew – default skew, #delay, and #1step

• How clocking blocks align signal access with simulation event regions

• Using clocking blocks inside interfaces for cleaner, modular testbenches

• Real-world examples to see it all in action

By the end of this lecture, you will be able to:
-Define and use clocking blocks to align signal timing with clock edges
-Avoid race conditions between driver and DUT
-Specify skew to control signal access precisely
-Use clocking blocks effectively in procedural blocks and interfaces
- Write more synchronized, maintainable, and industry-standard SystemVerilog testbenches

This session gives very good overview of what SV Assertions are, why to use them and how to write effectively in design or testbench environment

Events in System Verilog - This session will help you to understand what system Verilog Events are, why they are useful in simulation and how we an use them in verification environments.

In this video, we dive into the program block in SystemVerilog—an important construct used to model testbenches in a controlled and race-free manner. Learn:

-Why the program block was introduced

- Key differences between module and program

- How it helps avoid race conditions in simulations

- Practical syntax and coding examples

This lecture explains SystemVerilog subroutines – Tasks and Functions, focusing on the key enhancements introduced in SystemVerilog compared to Verilog.

Subroutines are heavily used in design, testbench, and verification code, and understanding their enhancements is critical for VLSI Design Verification roles.

Topics Covered in This Lecture:

• What are subroutines in SystemVerilog?

• Difference between tasks and functions

• Limitations of Verilog tasks/functions

• SystemVerilog enhancements in tasks and functions:

  • Automatic vs static lifetime

  • Input, output, and ref arguments

  • Default argument values

  • Void functions

  • Functions with timing (allowed in SV)

  • Passing arrays, structures, and classes

• Practical examples of SystemVerilog functions

• How these features are used in real verification environments