System on Chip Design using VIVADO and ZYBO Z7-10

Name: System on Chip Design using VIVADO and ZYBO Z7-10
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System on Chip Design using Digilent SOC Development Board ZYBO Z7-10

Created byProf. Dr. Academic Educator

Last updated 5/2021

English

What you'll learn

System on Chip Design using VIVADO and ZYBO Z7-10

Course content

6 sections • 21 lectures • 9h 3m total length

Course Outline4:41
The outline of the course is provided

ZYNQ SOC Hardware Design Using VIVADO26:13
In this lecture, we give an example which explains the creation of a zynq system using XILINX VIVADO.
Programming Processor Side Using SDK Tool15:54
This is a continuation of the previous lecture. In this lecture, we program the processor side using SDK tool. The hardware is designed in the previous lecture.
Creating ZYNQ System Employing Interrupts31:49
In this lecture, we explain how to create a ZYNQ system involving interrupts. The designed system is tested with ZYBO Z7-10 boards.
Creating ZYNQ System Employing AXI Timer Interrupt22:52
In this lecture, we create a ZYNQ system employing AXI timer interrupt.

Introduction to Vivado High Level Synthesis (HLS)25:49
Introductory information about Vivado HLS is provided in this lecture.
Steps of High-Level Synthesis Process14:48
In this lecture, we explain the steps of high level synthesis process performed by Vivado HLS
Project Creation in Vivado HLS and C/RTL CoSimulation35:52
In this lecture, we show how to create a project in Vivado HLS and perform C/RTL CoSimulation
Arbitrary Precision Data Types Used In VIvado HLS32:15
In this lecture, we deal with the data types supported by Vivado HLS.
HLS Interface Specification and Synthesis35:45
In this lecture, we provide information about HLS Interface Specification and Synthesis, such as creation of ports and association of port protocols to created ports and type of port protocols and their properties.
HLS Metrics and Pipelining Operation38:37
In this lecture, we provide information about HLS performance metrics and explain the pipelining operation which is very critical subject for efficient hardware implementation considering the performance metrics latency, resource utilization, and throughput.
Loop and array optimization for hardware implementation in Vivado HLS28:18
In this lecture, we provide information about how to optimize loops and arrays before implementing them in hardware.
Creating multiple solutions in HLS and solution optimization29:53
In this lecture, using VIVADO HLS, we show how to create and optimize the solutions using directives

Requirements

The VHDL knowledge can be a plus

Description

In this course, we will first provide basic information about system on chips, then SOC design examples will be provided using Vivado and Digilent ZYBO Z7-10 system on chip development board where XILINX ZYNQ 7000 system on chip is available. We will provide a number of practical applications using ZYBO Z7-10 illustrating the SOC design subject. We will also provide information about ZYNQ-7000 system on chip device.

Who this course is for:

All the engineering students interested in System on Chip Design

System on Chip Design using VIVADO and ZYBO Z7-10

What you'll learn

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Course content

Outline1 lecture • 5min

Introduction to System on Chips3 lectures • 1hr 33min

System On Chip Design (SOC) Using XILINX VIVADO using ZYBO Z7-104 lectures • 1hr 37min

Vivado High Level Synthesis (HLS)8 lectures • 4hr 1min

Creating IP using HDL, Vivado HLS, and Matlab HDL Coder3 lectures • 1hr 16min

Importing IP-cores to IP-catalog, and audio codec IP-core2 lectures • 32min

Requirements

Description

Who this course is for: