
(1) Design Metrics
(2) System Design Technology
(1) Fixed-Function IC
(2) Advantages
(3) Disadvantages
(1) Full Custom ASIC Technology
(2) Advantages
(3) Disadvantages
(1) Semi-Custom ASIC Technology
(2) Advantages
(3) Disadvantages
(1) HDL Role in Design Cycle
(2) Simulation Tool
(3) Synthesis Tool
(4) Place & Route Tool
(1) PLA
(2) Example of PLA Implementation
(1) PAL
(2) Example of PAL Implementation
(1) PAL with Storing Element
(1) CPLD
(2) CPLD Architecture
(3) Implementation Example
(1) FPGA
(2) Rooting Algorithm
(1) Implementation of Logic in FPGA (Example-1)
(2) Implementation of Logic in FPGA (Example-2)
(3) Implementation of Logic in FPGA (Example-3)
(1) Hardware description language
(2) History of VHDL
(1) Structure of VHDL Entity
(3) Identifiers
(4) Keywords
(1) Data Object (Constant Class)
(2) Examples of constant declaration
(1) Data Object (Variable Class)
(2) Examples of Variable declaration
(1) Data Object (Signal Class)
(2) Examples of Signal declaration
(1) Data Type
(i) Scalar Types (Enumeration Type)
(2) Examples of Enumeration Type declaration
(3) Examples of Enumeration Type object declaration
(1) Data Type
(i) Scalar Types (Integer Type)
(ii) Scalar Types (Floating Point Type)
(1) Data Type
(i) Scalar Types (Physical Type)
(1) Data Type
(i) Composite Type (Constraint Array Type)
(ii) Examples of Constraint array type declarations
(iii) Examples of object declaration of Constraint array type
(1) Data Type
(i) Composite Type (Un-Constraint Array Type)
(ii) Examples of Un-Constraint array type declarations
(iii) Examples of object declaration of Un-Constraint array type
(1) Data Type
(i) Composite Type (Record Type)
(ii) Examples of Record type declarations
(iii) Examples of object declaration of Record type
(1) Logical Operators
(2) Examples
(3) Software Demonstration
(1) Relational Operators
(2) Examples
(3) Software Demonstration
(1) Shift Operators
(2) sll and srl
(3) Examples
(4) Software Demonstration
(1) Shift Operators
(2) sla and sra
(3) Examples
(4) Software Demonstration
(1) Shift Operators
(2) rol and ror
(3) Examples
(4) Software Demonstration
(1) + (Addition Operator)
(2) - (Subtraction Operator)
(3) & (Concatenation Operator)
(4) Examples
(5) Software Demonstration
(1) * (multiplication Operator)
(2) / (division Operator)
(3) Examples
(4) Software Demonstration
1) mod (modulus Operator)
(2) rem (remainder Operator)
(3) Examples
(4) Software Demonstration
(1) Review
(2) Behaviour model of AND gate
(1) Behaviour model Example
(1) Example-1: Write behaviour model of Half Adder
(2) Example-2: Write behaviour model of Full Adder
(3) Full Adder Behaviour Model Software Demonstration
(1) Test bench
(2) Example-1 Testbench of “and gate” (using Explicit Association)
(3) Example-2 Testbench of “and gate” (using Positional Association)
(4) Software Demonstration
(1) Testbench of Half Adder
(2) Testbench of Full Adder
(3) Software Demonstration
(1) Behavior Model – Using Signals
(2) Behavior Model – Using Variables
(1) Write behaviour model of Full Adder (Alternate Code)
(2) Full Adder Testbench
(3) Software Demonstration
(1) Behavior model of 2 to 1 Multiplexer
(2) Testbench
(3) Software Demonstration
(1) Behavior model of one bit comparator
(2) Test bench
(3) Software Demonstration
(1) Behavior model of 2 to 4 Decoder
(2) Test bench
(3) Software demonstration
(1) Sequential Control Statements
(2) Various forms of if statements
(1) Basic form of if statement
(2) Level Triggered D Flip Flop using “if-else” statement
(3) Test bench
(4) Software Demonstration
(1) “if-else” statement
(2) 2 to 1 Multiplexer using “if-else” statement
(3) Test bench
(4) Software Demonstration
(1) if-elsif statement
(2) 4 to 1 Multiplexer model using “if-elsif” statement
(3) Test bench
(4) Software Demonstration
(1) Half Adder using “if-else” statements
(2) Test bench
(3) Software Demonstration
(1) Full Adder using “if-else” statements
(2) Test bench
(3) Software Demonstration
(1) Behavior model of one bit comparator using “if-else” statements
(2) Test bench
(3) Software Demonstration
(1) Behavior model of two bit comparator using “if-else” statements
(2) Test bench
(3) Software Demonstration
(1) Sequential Statements
(2) Introduction to Case Statement
(1) 2 to 1 Multiplexer using “case” Statement
(2) Test bench
(3) Software Demonstration
(1) 4 to 1 Multiplexer using “case” statement
(2) Test bench
(3) Software Demonstration
(1) 1-Bit Comparator using “case” statement
(2) Test bench
(3) Software Demonstration
(1) 2 to 4 Decoder using “case” statement
(2) Test bench
(3) Software Demonstration
(1) Half Adder using “case” statement
(2) Test bench
(3) Software Demonstration
(1) Data flow model of “AND” Gate
(2) Test bench
(3) Software Demonstration
(1) Data flow model of “Half Adder”
(2) Testbench
(3) Data flow model of “Full Adder”
(4) Testbench
(1) Data flow model of “Full Adder” Alternate Method
(2) Testbench
(3) Simulation Result
(1) Data flow model of 2-to-4 Decoder
(2) Testbench
(3) Simulation Result
(1) Conditional Signal Assignment Statement
(2) Data flow model of 2-to-1 Mux using Conditional Signal Assignment Statement
(3) Testbench
(4) Simulation Result
(1) Data flow model of 4-to-1 Multiplexer using Conditional Signal Assignment Statement
(2) Testbench
(3) Simulation Result
(1) Data flow model of 1-Bit Comparator using Conditional Signal Assignment Statement
(2) Testbench
(3) Simulation Result
(1) Select Signal Assignment Statement
(2) Data flow model of 2-to-1 Multiplexer
(3) Testbench
(4) Simulation Result
(1) Data flow model of 4-to-1 Multiplexer using Select Signal Assignment Statement
(2) Testbench
(3) Simulation Result
(1) Data flow model of 1-Bit Comparator using Select Signal Assignment Statement
(2) Testbench
(3) Simulation Result
Introduction to Structure Model
(1) Structure Model of Half Adder
(2) Testbench
(3) Simulation Result
(1) Structure Model of Full Adder
(2) Testbench
(3) Simulation Result
(1) Structure Model of 2 to 1 Multiplexer
(2) Testbench
(3) Simulation Result
(1) Structure Model of 2 to 4 Decoder
(2) Testbench
(3) Simulation Result
(1) Structure Model of 1-Bit Comparator
(2) Testbench
(3) Simulation Result
(1) Structure Model of 3-Bit Adder
(2) Testbench
(3) Simulation Result
(1) Structure Model of 4 to 1 Multiplexer using 2 to 1 Multiplexer
(2) Testbench
(3) Simulation Result
(1) Behavior Model of Negative Edge Triggered D Flip Flop
(2) Testbench
(3) Simulation Result
(1) Behavior Model of Negative Edge Triggered D Flip Flop
(2) Testbench
(3) Simulation Result
(1) Behavior Model of Negative edge triggered JK Flip Flop
(2) Testbench
(3) Simulation Result
(1) Behavior Model of Negative edge triggered JK Flip Flop
(2) Testbench
(3) Simulation Result
(1) Behavior Model of Negative edge triggered T Flip Flop
(2) Testbench
(3) Simulation Result
(1) Behavior Model of Parallel in Parallel out Register
(2) Testbench
(3) Simulation Result
(1) Structure Model of Parallel in Parallel out Register
(2) Testbench
(3) Simulation Result
(1) Behavior Model of Serial in Parallel out Register
(2) Testbench
(3) Simulation Result
(1) Structure Model of Serial in Parallel out Register
(2) Testbench
(3) Simulation Result
(1) Structure Model of Serial in Serial out Register
(2) Testbench
(3) Simulation Result
(1) Behavior Model of Serial in Serial out Register
(2) Testbench
(3) Simulation Result
(1) VHDL Code of 3 Bit Up Counter
(2) VHDL Code of 3 Bit Down Counter
(3) VHDL Code of 3 Bit Up-Down Counter
(4) Test Bench
(5) Software Demonstration
After completion of this course learners will be able to:
(1) Understand the concepts of design metrics which are to be optimized by a design engineer
(2) Understand the concepts of IC design technology
(3) Understand the implementation of logic using Fixed Function IC Technology, Full Custom ASIC Technology, and Semi-Custom ASIC Technology
(4) Understand the advantages and disadvantages of implementation of logic using Fixed Function IC Technology, Full Custom ASIC Technology, and Semi-Custom ASIC Technology
(5) Understand the concept of implementation of logic in PLAs, PALs, and CPLDs
(6) Understand the concept of implementation of logic in FPGAs
(7) Understand the IC design flow
(8) Understand the role of HDL in system design
(9) Understand the concepts of various VHDL constructs
(10) Understand various operators and their uses in VHDL coding
(11) Understand how to use Xilinx software for writing a VHDL code
(12) Understand how to use Xilinx software for simulating a VHDL code
(13) Understand how to use Xilinx software for implementing a VHDL code
(14) Implement combinational logic by using a behavioral modeling style
(15) Implement combinational logic by using a dataflow modeling style
(16) Implement combinational logic by using a structural modeling style
(17) Implement sequential logic by using a behavioral modeling style
(18) Implement sequential logic by using a structural modeling style