VHDL Circuit Design and FPGAs with VIVADO and MODELSIM

Name: VHDL Circuit Design and FPGAs with VIVADO and MODELSIM
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Circuit Design Using VHDL for FPGA Devices

Created byProf. Dr. Academic Educator

Last updated 3/2022

English

What you'll learn

Synthesizable VHDL Circuit Design and FPGA programming using VHDL
VHDL Language for Digital Circuit Design
Simulation and Synthesis Using VIVADO
Simulation of VHDL Implementations Using MODELSIM
FPGA Programming

Course content

13 sections • 56 lectures • 18h 54m total length

Outline4:05
Course outline is briefly explained

ENTITY in VHDL13:27
ENTITY module in VHDL is explained by example.
ARCHITECTURE in VHDL22:21
Architecture unit in VHDL is explained by examples.
Data Objects in VHDL17:07
Data objects, such as signal, constant, variable are explained by examples.
VIVADO Application: Creating I/O Ports for Different Data Types and Port Pin Num29:08
In this lecture, we explain how to create ports using VIVADO using the entity unit such that the required number of ports are created without wasting the resources.
Data types20:03
Data types are explained by examples.
VIVADO Application: Negative Numbers in VHDL, Positive and Natural Numbers33:56
In this lecture, we inspect 'natural' and 'positive' data types in VIVADO, and elaborate 2's complement representation of negative numbers in VHDL using VIVADO, furthermore, default values of data types are inspected in VIVADO.
VHDL Operators, assignment operators, logical ops, logical and arithmetic ops23:55
VHDL Operators such as ·assignment Operators, logical Operators, logical and arithmetic shift operators are explained.
VIVADO Application: Shift operators and abs() function simulation in VIVADO40:48
In this lecture, we simulate the operators 'SLL', 'SLA', 'SRL', 'SRA', 'ABS' in VIVADO for different data types.
VHDL Operators, rem, mod, rem, abs, &, **22:29
VHDL Operators, rem, mod, rem, abs, &, ** are explained by examples
Generic Statement7:51
The use of 'generic' statement in VHDL is explained by examples.
VIVADO Application: Power operator **, rem() and mod() simulation in VIVADO30:12
In this lecture, we simulate the power operator '**', and the remainder functions mod(), rem() in VIVADO. Besides, we simulate a simple concurrent VHDL code in VIVADO.

When and With-Select Statements14:02
Combinational circuit design using "when" and "with-select" statements is explained by examples.
VHDL Generate Statement14:40
The VHDL Statement "Generate" is explained by examples
VIVADO Application: Generate Statement, MUX 2x1 and When-Else statement44:25
In this lecture, we perform VIVADO simulations for the VHDL programs involving 'generate', 'when-else' statements. We consider the simulations of 'parity generator', 'vector reversal', 'MUX 2x1', and combinational circuit involving MUX 2x1 VHDL programs.
MUXES in VHDL, Part-120:42
Implementation of MUXES and circuits involving MUXES in VHDL is explained by examples.
MUXES in VHDL, Part-222:18
VHDL implementation of logic circuits involving MUXES is explained by examples.
VIVADO Application: IO Planning Using Vivado35:28
In this lecture we show how to assign FPGA pins to the entity ports. We show how to create a simple constraint file.
MUXES in VHDL, Part-312:46
VHDL implementation of logic circuits involving MUXES is explained by examples.
Binary Encoders in VHDL30:03
Gray, BCD, Octal, and binary Prority Encoders are implemented in VHDL
BCD Encoder and BCD to SS Display Converter in VHDL16:30
In this lecture BCD encoder and BCD to Sevent Segment Display Code Converter will be implemented in VHDL

Testbench writing for the simulation of VHDL programs22:57
In this lecture the students will learn how to write a testbench for the simulation of VHDL programs.
Example for testbench writing17:31
Testbench writing will be exaplained by an example
VIVADO Application: Writing TEST-BENCH and VIVADO Simulation Using TEST-BENCH30:19
In this lecture, we write a test-bench for a VHDL implementation, and simulate the VHDL implementation in VIVADO using the test-bench.

Simulation using modelsim, a basic example16:29
Simulation using modelsim, a basic example
ModelSim Simulation of VHDL Codes with TestBenches11:37
ModelSim Simulation of VHDL Codes with TestBenches
Displaying Signal Values Using Modelsim13:42
Displaying Signal Values Using Modelsim
Simulating VHDL Codes With Modelsim Without Using TestBenches9:55
Simulating VHDL Codes With Modelsim Without Using TestBenches

User defined data types and contrained arrays in VHDL20:05
In this lecture, user defined data types involving enumerated data types and constrained arrays are explained by examples.
Unconstrained arrays and port arrays19:17
In this lecture, unconstrained array definitions and use of the port arrays are explained by examples
Matrices and 3D arrays in VHDL35:58
In this lecture the definitions of matrices , 3D arrays and higher dimensional matrices and their use will be explained. How to access to the elements of arrays or matrices are explained by examples.
MODELSIM Simulation for user-defined data type attributes25:07
Attributes of user defined data types are explained using MODELSIM simulation

Process, if-then-else, D-flip flop in VHDL are explained16:14
In this lecture, the students will learn the implementation of sequential circuits in VHDL. Process, if-then-else statement, and D-flip flop implementation are explained.
JK Flip-Flop, T Flip-Flop, Counter and MUX implementation in VHDL using Process23:51
In this lecture, JK Flip-Flop, T Flip-Flop, Counter and MUX implementation in VHDL using Process are explained.
Clock divider digital circuits21:15
In this lecture, operations of digital circuits used for clock division operation are explained
Clock divider (frequency divider) implementation in VHDL19:44
In this lecture, implementation of clock divider or frequency divider in VHDL language is explained and various VHDL clock divider examples are provided.
SS Display Driver Implementation in VHDL11:12
In this lecture, we write the necessary VHDL codes to drive a seven segment display that shows the digits from 0 to 9 for one second duration each.
VIVADO Application: Parallel Operation, Signal Objects vs Variable Objects32:56
In this lecture, we explain the parallel processing concept using VIVADO, and compare the signal object to variable object considering the update delay of both objects.
MODELSIM Simulation of T type Flip-Flop17:53
Simulation of T Flip-Flop VHDL Implementation Using MODELSIM
MODELSIM Simulation: Signal Object Update is NOT Immediate15:08
Using MODELSIM simulation we show that signal object update is not immediate.
MODELSIM Simulation: Signal Object Behavior-219:12
We elaborate the update of the signal object more using MODELSIM.
MODELSIM Simulation: Clock Division in VHDL, Part-113:03
MODELSIM Simulation: Clock Division in VHDL, Part-1
MODELSIM Simulation: Clock Division in VHDL, Part-120:52
MODELSIM Simulation: Clock Division in VHDL, Part-1

Packages in VHDL10:07
In this lecture, we explain how to write a package and use it in our main program.
VIVADO Application: Package declaration and Its use in the main program.10:50
In this lecture, using VIVADO, we show how to create a package and use it in the main program.
Components in VHDL17:55
In this lecture, we show how to define a component and write a VHDL code using components.
VIVADO Application: Defining components and using them in VHDL codes19:03
Defining components and using them in VHDL codes using VIVADO is demonstrated.

Requirements

Digital logic design

Description

In this course, we will teach VHDL circuit design. The fundamental concepts about VHDL circuit design will be provided. In addition, practical examples using FPGA development boards will be provided. Combinational and clocked logic circuit design will be explained by examples. We will use either VIVADO or MODELSIM platform for the simulation and development of VHDL designs. Some of the written codes will be loaded into FPGA cards for demonstration purposes.

We use MODELSIM for simulation of the VHDL codes. In VHDL circuit design, good knowledge of signal and variable objects is necessary, and the engineer should know the differences between signal and variable objects very well. The most confusing part between the signal and variable objects is that variable objects are updated immediately whereas update of the signal objects is not immediate. Clock division operation and behavior of the signal and variable objects are explained in details using MODELSIM simulations. The behaviors of the combinational and sequential circuits are clarified using MODELSIM simulations.

We use VIVADO platform for simulation and circuit synthesis of the VHDL codes. In fact, it is better to use the MODELSIM platform for simulations and VIVADO platform for circuit synthesis and FPGA programming. We indicate that a VHDL code which can be simulated may not be synthesizable, and we explain this concept providing examples on VIVADO platform. Through the course, we provide many videos explaining VHDL language for circuit design and use of MODELSIM and VIVADO platforms for simulation and circuit synthesis.

Who this course is for:

Digital design engineers

VHDL Circuit Design and FPGAs with VIVADO and MODELSIM

What you'll learn

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Course content

Introduction1 lecture • 4min

Entity, Architecture and VHDL Operators11 lectures • 4hr 21min

Combinational Circuit Design in VHDL9 lectures • 3hr 31min

Simulation of VHDL Programs, and Testbench Writing3 lectures • 1hr 11min

Simulation Using MODELSIM4 lectures • 52min

User Defined Data Types, Constrained and Unconstrained Arrays, Matrices in VHDL4 lectures • 1hr 40min

Sequential circuits, process, clock divider, sample seq. circ. implementations11 lectures • 3hr 31min

VHDL Statements, Wait, Wait On, Wait Until, Wait For and CASE2 lectures • 18min

Loops in VHDL2 lectures • 38min

Packages, Components, Functions, Procedures4 lectures • 58min

Requirements

Description

Who this course is for: