SoC Design 2: Systemverilog Features for RTL Coding
3.9 (57 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
1,278 students enrolled

SoC Design 2: Systemverilog Features for RTL Coding

System Verilog Programming: Special Constructs for Design / RTL Coding in Systemverilog over Verilog
3.9 (57 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
1,278 students enrolled
Last updated 5/2019
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This course includes
  • 1 hour on-demand video
  • 1 article
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Be able to use Systemverilog extended features for RTL Coding
Requirements
  • Know about basics of coding in Systemverilog or Verilog.
  • Be able to write simple Systemverilog Programs
Description

This is a short, intermediate level course in Systemverilog HDL and it covers only the few specific topic in it which are useful in design /RTL coding. The objective of this course is to teach Systemverilog extensions to Verilog for RTL design coding which are widely used in the VLSI industry.

 Although,it is designed for learning SoC design coding rather than verification, verification engineers are also encouraged to enroll this, as all of them are useful in test-bench coding as well . This will teach below constructs.

  • Constants & Parameters

  • Parameterized  Modules

  • Functions & Tasks

  • Enumeration

  • Typedef

  • Structure

  • Interfaces & Modports

  • Generate Statements

If you are an expert, or someone who is already writing full fledged systemverilog RTL design code, this course is NOT for you. Also, if you are beginner to Verilog or Systemverilog, this course will NOT teach the basics of programming for those HDLs.

To  make this course effective for you, you must have the basic knowledge of either Verilog or Systemverilog. You should be able to write simple design and test bench programs in Verilog or Systemverilog, and simulate.

Who this course is for:
  • Someone who is already familiar with Systemverilog programming
  • SoC Design engineers not familiar with Systemverilog specific features useful in RTL coding
Course content
Expand all 27 lectures 01:05:30
+ Parameters & Constants in Systemverilog
3 lectures 05:09
The keyword 'parameter'
01:17
The keyword 'localparam'
01:29
+ Functions & Tasks
4 lectures 08:08
Functions
03:43
Verilog & Systemverilog Functions
01:04
Tasks
01:51
Pass by Reference
01:30
+ Enumeration , Structures & Typedef
3 lectures 06:08
Enumeration
02:28
Typedef
01:44
Structures
01:56
+ Design & TB Example using Structure, Enumeration & Parameter
3 lectures 11:21
Example_1_Specification
02:55
Example_1_Design
02:37
Example_1_TB
05:49
+ Interfaces
4 lectures 10:25
Interfaces
03:35
Modports
03:10
Connecting Modules with without Iinterface
01:27
Clocking Blocks
02:13
+ Generate Statement
5 lectures 10:56
Generate Statement
00:51
Loop Generate
04:18
Conditional Generate
01:43
Generate V/s Always
01:16
Design Hierarchy Example with Generate
02:48