SoC Design 1: Systemverilog Assignment Statements &Synthesis
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- Be able to map the circuit produced by the Systemverilog code you write
- Know about basics of coding in Systemverilog or Verilog.
- Be able to write simple Systemverilog Programs
This is a short, intermediate level course in Systemverilog HDL and it covers only the ONE specific topic in it, "the assignment statements". The objective of this course is to teach the different types of assignment statements in Verilog and Systemverilog, and to map them to the final circuit produced in the IC.
Although,it is designed for learning SoC design coding rather than verification, verification engineers are also encouraged to enroll this, as it is teaching one of the fundamental principal in a Hardware Description Language.
First, it teaches the different types of assignment statements in Verilog and Systemverilog, and their correct usage so that the intended circuit is generated by the HDL code after synthesis. It includes,
- Continuous assignments
- Procedural Assignments
- Blocking Assignment
- Non Blocking Assignments
All of them are explained specific to Verilog as well as Systemverilog. Also, the usage of all these statements to produce the basic digital circuits are explained, which are,
- Combinational circuits
- Sequential Circuits
- Flip Flop
Next it teaches the effect of adding flow control statements in the final circuit. Here you will learn what circuit components will be generated if you add,
- Branching Statements
- if-else, case
- Looping Statements
- for, while, do while
- Jumping Statements
- disable, break, continue, return
If you are an expert, or someone who is already able to map these statements to the circuits, this course is NOT for you. Also, if you are beginner to Verilog or Systemverilog, this course will NOT teach the basics of programming for those HDLs.
To make this course effective for you, you must have the basic knowledge of either Verilog or Systemverilog. You should be able to write simple design and test bench programs in Verilog or Systemverilog, and simulate. If you are not familiar with these, you are encouraged to enroll our basic level course titled "SystemVerilog Beginner: Write Your First Design &TB Modules".
- Someone who is already familiar with Systemverilog programming
- SV programmers confused with blocking and nonblocking of assignments usage
- SoC Designers looking for knowing circuit produced in the final IC using different types of assignment statements in SV.