SoC Design 1: Systemverilog Assignment Statements &Synthesis
4.0 (68 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
1,027 students enrolled

SoC Design 1: Systemverilog Assignment Statements &Synthesis

Verilog / System Verilog Programs to circuits : Continuous, procedural, blocking & non blocking assignments
4.0 (68 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
1,027 students enrolled
Last updated 5/2019
English
English [Auto-generated]
Current price: $34.99 Original price: $49.99 Discount: 30% off
5 hours left at this price!
30-Day Money-Back Guarantee
This course includes
  • 1 hour on-demand video
  • 1 article
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
Training 5 or more people?

Get your team access to 4,000+ top Udemy courses anytime, anywhere.

Try Udemy for Business
What you'll learn
  • Be able to map the circuit produced by the Systemverilog code you write
Requirements
  • Know about basics of coding in Systemverilog or Verilog.
  • Be able to write simple Systemverilog Programs
Description

This is a short, intermediate level course in Systemverilog HDL and it covers only the ONE specific topic in it, "the assignment statements". The objective of this course is to teach the different types of assignment statements in Verilog and Systemverilog, and to map them to the final circuit produced in the IC.

 Although,it is designed for learning SoC design coding rather than verification, verification engineers are also encouraged to enroll this, as it is teaching one of the fundamental principal in a Hardware Description Language. 

First, it teaches the different types of assignment statements in Verilog and Systemverilog, and their correct usage so that the intended circuit is generated by the HDL code after synthesis. It includes,

  • Continuous assignments
  • Procedural Assignments
    • Blocking Assignment
    • Non Blocking Assignments 

All of them are explained specific to Verilog as well as Systemverilog. Also, the usage of all these statements to produce the basic digital circuits are explained,  which are,

  • Combinational circuits
  • Sequential Circuits
    • Flip Flop
    • Latch

Next it teaches the effect of adding flow control statements in the final circuit. Here you will learn what circuit components will be generated if you add, 

  • Branching Statements
    • if-else, case
  • Looping Statements
    • for, while, do while
  • Jumping Statements
    • disable, break, continue, return 

If you are an expert, or someone who is already able to map these statements to the circuits, this course is NOT for you. Also, if you are beginner to Verilog or Systemverilog, this course will NOT teach the basics of programming for those HDLs.

To  make this course effective for you, you must have the basic knowledge of either Verilog or Systemverilog. You should be able to write simple design and test bench programs in Verilog or Systemverilog, and simulate. If you are not familiar with these, you are encouraged to enroll our basic level course titled "SystemVerilog Beginner:  Write Your First Design &TB Modules".

Who this course is for:
  • Someone who is already familiar with Systemverilog programming
  • SV programmers confused with blocking and nonblocking of assignments usage
  • SoC Designers looking for knowing circuit produced in the final IC using different types of assignment statements in SV.
Course content
Expand all 23 lectures 54:08
+ Always Block in Systemverilog
6 lectures 09:55
Always Block in Systemverilog
00:54
The always_comb Block
01:46
always_comb V/S always @*
01:54
Example of using always_comb
02:15
The always_latch Block
01:48
The always_ff Block
01:18
+ Blocking and Non-Blocking Assignments
5 lectures 11:33
Blocking and Non-Blocking Assignments
01:52
BA & NBA in Simulation
03:37
BA & NBA in Synthesis
02:23
BA & NBA Synthesis Examples
02:30
Guidelines for using Blocking and Non Blocking Assignments
01:11
+ Effect of Flow control Statements in the Circuit after Synthesis
4 lectures 11:40
Branching Statements in Synthesis
05:46
Branching Statement - Case
01:04
Looping Statements in Synthesis
02:27
Jumping Statements in Synthesis
02:23
+ Summary
3 lectures 07:52
Summary
02:22
Bonus Lecture
00:33