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State Machines and VHDL Implementation of State Machines
Rating: 4.0 out of 5(17 ratings)
151 students
Created byProf. Dr. Academic Educator
Last updated 4/2022
English

What you'll learn

  • State Machines
  • VHDL Implementation of State Machines
  • Timed State Machines
  • VHDL Implementation of Timed State Machines

Course content

1 section • 18 lectures • 4h 44m total length

  • Outline for the State Machines and VHDL Implementation of State Machines8:56

    The outline of the course is given and motivation of the course is explained.

  • General view of State Machines, Mealy and Moore State Machines17:14

    Meally and Moore state machines will be explained with solved examples.

  • Conversion of a Mealy state machine to a Moore state machine10:12

    In this lecture, we will learn how to convert a Mealy state machine to a Moore state machine

  • Conversion of a Moore state machine to a Mealy state machine7:41

    In this lecture, we explain how to convert a Moore state machine to a Mealy state machine

  • Designing a state machine for "011" sequence detection12:27

    The state machine of a sequence detector is explained in an example.

  • State machines for bit stuffing, edge detector and elevator control circuits18:42

    In this lecture, state machines of bit stuffing, edge detector and elevator control circuits are obtained.

  • State machines for Manchester encoding and obstacle avoidance robot are obtained22:09

    In this lecture, we explained how to obtain the state diagrams for  Manchester encoding and obstacle avoidance robot.

  • State machines for RS-232 signaling, non return to zero inverted encoding16:43

    State machines for RS-232 signaling, non return to zero inverted encoding and non regular counter are obtained.

  • VHDL Templates are given for the Implementation of State Machines18:51

    In this lecture, we provide VHDL templates for the implementation of state machines and explain their usage.

  • Implementation of a 3-bit counter in VHDL using Moore state machines14:26

    In this lecture, implementation of a 3-bit counter will be done in VHDL using state machines. The VHDL implementation will be explained in a step-wise manner.

  • MODELSIM SIMULATION: Simulation of 3-bit counter state machine using MODELSIM15:19

    In this lecture we show how to simulate the state machine of 3-bit counter using MODELSIM

  • Analysis of 3-bit counter state machine (in VHDL)26:18

    In this lecture, we analyse the  flow of the VHDL program written for the implementation of 3-bit binary counter.

  • Implementation of a Mealy state machine in VHDL16:24

    In this lecture, we provide an example for the implementation of a Mealy state machine in VHDL language.

  • MODELSIM Simulation: Simulation of Mealy State Machine Using MODELSIM16:31

    In this lecture we show how to simulate a Mealy state machine implementation using MODELSIM. We use  testbench for the simulation of VHDL implementation using MODELSIM.

  • Introduction to timed state machines9:13

    The meaning of timed state machines is explained.

  • The VHDL template for the implementation of timed state machines12:43

    In this lecture, we deliver the VHDL template for the implementation of timed state machines and explain its usage.

  • An example for the VHDL implementation of a timed state machine18:28

    In this lecture, we provide an example for the VHDL implementation of a timed state machine. We do the implementation in steps and explain every part clearly.

  • MODELSIM Simulation: Simulation of Timed State Machine22:24

    In this lecture, we explain how to simulate a timed state machine using MODELSIM.

Requirements

  • The students should have basic knowledge in digital logic circuit design

Description

In this course, the students will get information about the state machines and VHDL implementation of state machines. We first give information about the Mealy and Moore state machines and solve some problems about the state machine characterization of real life and mathematical problems. Then, VHDL programming of state machines is taught.

Who this course is for:

  • Electronic hardware engineers, and computer engineering students, everyone interested in VHDL programming of FPGA chips

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