State Machines and VHDL Implementation of State Machines
3.6 (6 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
47 students enrolled

State Machines and VHDL Implementation of State Machines

State Machines and VHDL programming
3.6 (6 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
47 students enrolled
Last updated 4/2020
English
Current price: $13.99 Original price: $19.99 Discount: 30% off
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This course includes
  • 4 hours on-demand video
  • 14 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • State Machines and VHDL Programming of State Machines
Requirements
  • The students should have basic knowledge in digital logic circuit design
Description

In this course, the students will get information about the state machines and VHDL implementation of state machines. We first give information about the Mealy and Moore state machines and solve some problems about the state machine characterization of real life and mathematical problems. Then, VHDL programming of state machines is taught.

Who this course is for:
  • Electronic hardware engineers, and computer engineering students, everyone interested in VHDL programming of FPGA chips
Course content
Expand 15 lectures 03:50:27
+ Introduction to State Machines and VHDL Implementation of State Machines
15 lectures 03:50:27

The outline of the course is given and motivation of the course is explained.

Preview 08:56

Meally and Moore state machines will be explained with solved examples.

Preview 17:14

In this lecture, we will learn how to convert a Mealy state machine to a Moore state machine

Conversion of a Mealy state machine to a Moore state machine
10:12

In this lecture, we explain how to convert a Moore state machine to a Mealy state machine

Conversion of a Moore state machine to a Mealy state machine
07:41

The state machine of a sequence detector is explained in an example.

Designing a state machine for "011" sequence detection
12:27

In this lecture, state machines of bit stuffing, edge detector and elevator control circuits are obtained.

State machines for bit stuffing, edge detector and elevator control circuits
18:42

In this lecture, we explained how to obtain the state diagrams for  Manchester encoding and obstacle avoidance robot.

State machines for Manchester encoding and obstacle avoidance robot are obtained
22:09

State machines for RS-232 signaling, non return to zero inverted encoding and non regular counter are obtained.

State machines for RS-232 signaling, non return to zero inverted encoding
16:43

In this lecture, we provide VHDL templates for the implementation of state machines and explain their usage.

VHDL Templates are given for the Implementation of State Machines
18:51

In this lecture, implementation of a 3-bit counter will be done in VHDL using state machines. The VHDL implementation will be explained in a step-wise manner.

Implementation of a 3-bit counter in VHDL using Moore state machines
14:26

In this lecture, we analyse the  flow of the VHDL program written for the implementation of 3-bit binary counter.

Analysis of 3-bit counter state machine (in VHDL)
26:18

In this lecture, we provide an example for the implementation of a Mealy state machine in VHDL language.

Implementation of a Mealy state machine in VHDL
16:24

The meaning of timed state machines is explained.

Introduction to timed state machines
09:13

In this lecture, we deliver the VHDL template for the implementation of timed state machines and explain its usage.

The VHDL template for the implementation of timed state machines
12:43

In this lecture, we provide an example for the VHDL implementation of a timed state machine. We do the implementation in steps and explain every part clearly.

An example for the VHDL implementation of a timed state machine
18:28