SOC Verification using SystemVerilog

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language
Rating: 4.3 out of 5 (4,383 ratings)
36,684 students
SOC Verification using SystemVerilog
Rating: 4.3 out of 5 (4,383 ratings)
36,684 students
Learn the important concepts in SOC/ASIC/VLSI design verification flow
Learn the System Verilog language for Functional Verification usage
Be ready and qualified for a Verification job in semiconductor industry
Udemy Certification on successful course completion
Be able to code, simulate and verify SystemVerilog Testbenches


  • Basic digital design or awareness to chip design flows
  • Passion for learning

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.

Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course

Who this course is for:
  • Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry
  • Digital Design and Verification Professionals who are passionate about continuous learning
Course content
9 sections • 35 lectures • 4h 15m total length
  • Introduction and Overview
  • Introduction to SOC and VLSI design flows
  • Course Resources
    1 page
  • Testing Awareness before we start
    4 questions
  • Verification - What, Why and How ?
  • Verification - Planning, Approaches, Metrics
  • Verification Methodologies - Simulation, Formal, Assertions
  • Directed vs Constrained Random Verification - Coverage
  • Other Trends - HW+SW Verification, Emulation
  • Test your Verification Concepts now
    5 questions
  • History and Language usage overview
  • Language Constructs - Data types and Operators
  • Language Constructs - Loops and Control Flows
  • Tasks and Functions
  • Arrays and Queues
  • Test Your System Verilog Language Basics now
    5 questions
  • Interfaces
  • Clocking Blocks
  • Program Blocks
  • Direct Programming Interface (DPI)
    4 pages
  • Test - How much more you know now !
    4 questions
  • Basic OOP Concepts
  • System Verilog Classes Explained
  • Virtual Interfaces
  • Random Constraints and usages - Part 1
  • Random Constraints - Part 2
  • Test - What have you learned more now ?
    5 questions
  • Processes and Threads in System Verilog
  • System Verilog Mailboxes
  • Synchronization - Events and Semaphores
  • Test your knowledge now on Advanced System Verilog
    4 questions
  • Exercise 1: Case Study on a Design to be verified
  • Exercise 2: Coding exercise to build a Design to be Verified OR Review example
    5 pages
  • Exercise 3: Coding Interfaces and Clocking Blocks to connect
    2 pages
  • Exercise 4: Building Class based Testbench components
    7 pages
  • Exercise 5: Connecting all TB components using mailboxes
    7 pages
  • Exercise 6: Build the top TB with DUT, compile and simulate
    6 pages
  • Standard Verification Methodologies - Need and evolution
  • Introduction to concept of OVM and UVM
  • Summary and learnings and future topics
  • Course Improvement Survey
  • Final Test - Are you ready for a Verification Job now?
    2 questions

Expert Verification Engr, Intel Alumni, 18+ yrs exp, Author
Ramdas Mozhikunnath M
  • 4.3 Instructor Rating
  • 7,754 Reviews
  • 50,988 Students
  • 4 Courses

Experienced and Passionate Verification Engineer with 18+ years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups.

Co-Author of book "Cracking Digital VLSI Verification Interviews: Interview Success" available on Amazon

Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others

Quora Top Writer 2017 ,2018 in VLSI/Semiconductor topics