SOC Verification using SystemVerilog
- Basic digital design or awareness to chip design flows
- Passion for learning
This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.
Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course
Who this course is for:
- Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry
- Digital Design and Verification Professionals who are passionate about continuous learning
- 04:15Introduction and Overview
- 05:00Introduction to SOC and VLSI design flows
- 1 pageCourse Resources
- 4 questionsTesting Awareness before we start
Experienced and Passionate Verification Engineer with 18+ years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups.
Co-Author of book "Cracking Digital VLSI Verification Interviews: Interview Success" available on Amazon
Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others
Quora Top Writer 2017 ,2018 in VLSI/Semiconductor topics