RTL Fundamentals in System Verilog

Install Docker on Windows using WSL 2, noting version differences. Install Ubuntu 20.04 from the Microsoft Store, verify WSL with PowerShell, then start Docker Desktop and confirm it runs.

Docker images reside in hub.docker.com; search Silicon Bootcamp images and pull a 2024 Vivado subset. Windows PowerShell example shows a 2 GB download and 5.5 GB XM dash synth image.

Enter the Ubuntu container, run the test install.sh script to simulate and synthesize a small design, and use Gtkwave to visualize the clock waveform.

Explore EDA playground to simulate digital logic in a web browser using server-based simulators with GitHub code access and local save, while noting runtime limits and downtime.

Trace the evolution of compute machines from mechanical to electronic circuits and learn how RTL models the combinational logic between storage elements, via synthesis tools.

Explore RTL abstraction in combinational and memory elements, where outputs depend on past inputs via clocks, with flip-flops and registers, and HDLs like Verilog, SystemVerilog, VHDL.

Explore the synthesizable subset of SystemVerilog, its role as a Verilog superset, and new data types and verification constructs that clarify rtl design and catch errors early.

Define the synthesizable subset of SystemVerilog for RTL that can synthesize into hardware with logic gates and flip-flops. Introduce modules, signals, bit vectors, procedural blocks, continuous assignments, and event expressions.

Define a module to encapsulate rtl functionality, parameterize inputs and outputs, instantiate it within other modules to compose, and use signals, four-state logic 01X and Z, and bit-vector slices.

Learn procedural blocks in RTL SystemVerilog, including logic and reg assignments, and distinguish synthesizable always blocks from non-synthesizable initial and final blocks; explore always_comb and always_latch for combinational logic.

Explore synthesizable always blocks in SystemVerilog for logic design. Use always_ff for flip-flops and non-blocking assignments to model positive edge-triggered memory.

Explore continuous assignments as an alternative to describe combinational logic in RTL, using the assign keyword with logic or wire types and modeling with the ternary operator.

Explore event expressions that trigger always blocks in system verilog, using A or B for combinational logic and a clock’s positive edge to infer flip flops.

Enforce the single assignment rule in rtl fundamentals in SystemVerilog: drive a signal with one procedural block or one continuous assignment, and do so at compile time.

Explore how misusing constructs from the synthesizable subset breaches a rule, preventing the synthesis tool from building logic gates, and note that implicit timing controls and tasks are illegal.

Explore rtl fundamentals in SystemVerilog through an n-bit ripple adder module with a parameterized width, concatenating carry out and sum, using logic data types.

Begin RTL implementation by defining a systemverilog function for a half adder that returns a two-bit logic vector; carryout comes from A and B AND, sum from A XOR B.

Build a full adder from half adders in SystemVerilog, with inputs A, B, carry in, and return a two-bit vector with sum in bit 0 and carry out in bit 1.

Cascade full adder stages to build the n-bit ripple adder using an n plus one carry vector, a generate block with a loop, and a two-bit result array per stage.

Define a parameterized testbench wrapper that instantiates ripple adder, uses bit inputs and logic outputs to detect X, connects S and C_out, and exposes expected sum and a fail flag.

Explore rtl fundamentals in system verilog with a testbench that validates a hardware adder against a plus b reference model using random stimulus via $urandom_range across 100 iterations.

Learn to run a docker container on macOS with GUI display, using xhost +, to access the RTL design and testbench, and generate simulation and synthesis scripts with Ninja Scripts.

Explore RTL simulation using the sim script for a single module and testbench, fix a misspelled local param keyword, and add a delay to advance time.

Operate the gtk wave viewer to inspect simulation waveforms from dump.vxd, adjust radix and data format, test an eight-bit adder, and then synthesize the RTL into hardware gates.

Explore rtl synthesis for a ripple adder on a fpga, mapping rtl to gate level hardware using configurable logic blocks, analyze max delay paths, and compare 4-bit versus 16-bit adders.

From the synthesis tool, the gate netlist in repl_addr_csv presents module instantiations of input buffers and LUTs, the configurable logic blocks that implement a repl adder.

Simulate the gate level netlist with gate smash, resolve parameter and time scale issues, align input width to 16 bits for ripple adder, and observe gate-level hierarchy in wave viewer.