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Mastering RISC-V Processor for Embedded Systems Programming

Name: Mastering RISC-V Processor for Embedded Systems Programming
Rating: 4.6 (60 reviews)

Revealing RISC-V Processor Architecture, C/Assembly Programming for RISC-V CPU, RISC-V Main Features, Debugging RISC-V

Created byWadix Technologies

Last updated 12/2025

English

English [Auto],

What you'll learn

Get to know RISCV Processor Architecture
Understand RISCV instruction Set and programming model
Learning how to write your first RISCV program
Hands on RISCV Hardware blocks like PMP for memory protection, Toolchain in use, Interrupts
Get a template RISCV makefile project

Course content

9 sections • 76 lectures • 5h 17m total length

Processors Market Overview2:00
Explore the embedded processor market, summarizing five key architectures - Intel x86, AMD Ryzen, MIPS, ARM with Cortex-M/R/A, and RISC-V - and note RISC-V's rise against ARM in low-power markets.
Processor Criteria5:19
Assess RISC-V processors for embedded systems using criteria including performance, power consumption, code size, scalability, ecosystem cost, tooling, and licensing to choose the right architecture for a given use case.
CISC vs RISC based Instructions Design3:03
Compare cisc and risc instruction design, showing how both rely on micro-operations, with risc using basic load/store instructions to ease decoding, while cisc uses more complex instructions broken into micro-operations.
CISC vs RISC Benchmarking3:42
ARM vs X86 Processors Architectures2:40
Compare x86 and ARM architectures with a benchmarking model; x86 dominates performance, while ARM leads in power, cost, and scalability across Cortex-A, Cortex-R, and Cortex-M, aided by compilers.
ARM Vs RISCV Architecture4:58
Compare risc-v and arm architectures, highlighting open licensing, easy customization, and lower integration cost for risc-v, plus a developing ecosystem with toolchain and ide support, while noting arm’s performance.
ARM and RISCV as Heterogeneous SOC Design2:07
Explore heterogeneous SoC design by integrating a mature ARM core in the application domain with a customized RISC-V subsystem that adds new instructions for audio, video, and machine learning tasks.

RISCV Instructions Set: Instructions Base Lines6:08
Explore baseline RISC-V instruction sets and extensions, covering RV32I, RV64I, RV128, and embedded e baseline targeting small devices with 16 registers, memory access, and weak memory ordering versus x86.
RISCV Instructions Set: Instructions Extensions4:00
Explore how compiler-injected instruction extensions enable optional hardware such as floating point units, dsp, and atomic instructions, and highlight toolchain alignment with execution modes in a RISC-V processor.
RISCV Assembly Pseudo Instructions1:13
Explore RISC-V assembly pseudo instructions to improve readability of low-level code. Learn how pseudo instructions translate to real RISC-V instructions and compile through the toolchain, making writing and memorization easier.
RISCV Instructions Set Summary1:12
Explore the RISC-V instruction set by comparing pseudo instructions with real base instructions, highlighting mnemonic meaning, readability, and how both representations achieve the same tasks.
RISCV Instructions: Arithmetic Operations1:00
RISC-V supports arithmetic operations such as additions and subtractions, conditional operations, and immediate load or program counter manipulation, with extensions adding multiply and divide units.
RISCV Instructions: Logical Operations3:44
Explore RISC-V logical operations, including and, or, and xor, with and without 12-bit immediates, and learn when to use registers for larger values and upcoming bitwise rotation support.
RISCV Instructions: Load/Store Memory Operations1:52
Explore how the RISC-V processor uses load and store instructions to read and write memory, supporting doubleword, word, halfword, and byte data with signed or unsigned options and 12-bit offset.
RISCV Instructions: Branch/Jump Operations2:45
Master RISC-V branching and jumping, covering conditional branches and jump and link with 20-bit immediates, plus 12-bit base-offset addressing updating the program counter and link register.
RISCV Instruction Format Encoding3:26
Explore four RISC-V instruction encoding formats—R, I, SB, and UJ—and how opcodes identify the instruction type while field positions determine destination and source registers, with five-bit indexing for 32 registers.
RISC-V vs ARM Architecture & RISC-V Instruction Set Fundamentals

RISCV General Purpose Registers: Zero, SP, RA, GP, TP Registers5:57
Identify the 32 general purpose registers in standard RISC-V, including x0 zero, x1 return address, x2 sp, x3 gp, and x4 tp; note the program counter is not a GPR.
RISCV General Purpose Registers: Temporary Registers (Caller Registers)2:08
RISC-V temporary registers up to seven are used by a function and may be overwritten. The caller must back up and restore these registers to preserve data on return.
RISCV General Purpose Registers: Saved Registers (Callee Registers)1:46
RISCV General Purpose Registers: Function Arguments Registers1:29
RISC-V uses eight general purpose registers to pass function arguments, enabling fast access without stack saves, a notable improvement over ARM Cortex-M’s four-parameter limit.
RISCV General Purpose Registers: Return Value Registers1:04
RISC-V general purpose registers x10 and x11 hold function return values, shared with arguments; allocate one register for 32-bit results or both for 64-bit results.
RISCV CSR Registers2:47
Explore how RISC-V control and status registers track processor state, interrupts, and exceptions, detailing mie, mtvec, mepc, mcause, mip, and mhartid for multi-core systems.
RISCV CSR Registers: Instructions to Access CSR Registers2:49
Explore how RISC-V CSR registers are accessed with two instruction categories: register-based operations that read, overwrite, set, or clear bits, and immediate-based operations that use five-bit immediates.
RISC-V Registers & CSRs Essentials

RISCV Modes Overview4:16
Learn about the three RISC-V modes—machine, supervisor, and user—and how mode switching enables isolation while a secure kernel in machine mode protects secret keys for OS and applications.
RISCV Modes : Machine Mode4:02
Explore machine mode as the highest privilege level in RISC-V, granting full access to control and status registers and default handling of interrupts, with delegation to supervisor mode when supported.
RISCV Modes : Supervisor Mode5:49
Explore how RISC-V supervisor mode offers higher privilege than user mode but less than machine mode, enabling selective access to csrs, delegation of interrupts, and banked csrs like scause.
RISCV Modes : User Mode1:30
RISC-V user mode is the lowest privileged level, restricting access to supervisor and machine mode registers, with only user mode csrs accessible; interrupts trap to machine or supervisor mode.
How to Determine the Current RISCV Execution Privilege Modes3:21
Determine the current RISC-V privilege mode by probing machine mode CSR access with mcause. If accessible, it is machine mode; otherwise use scause to differentiate supervisor from user mode.
How to Switch Between Different RISCV Privilege Modes5:15
Learn how ecall triggers internal exceptions and switches execution modes. Understand how mstatus, sstatus, mpp, and delegation determine returns via mret and sret.
RISCV Privilege Modes Configurations4:51
RISC-V Privilege Modes & Mode Switching (U/S/M)

PMP Functionalities Overview3:09
Explore how the RISC-V physical memory protection (PMP) checks fetch, read, and write accesses against defined memory regions with start addresses, lengths, and rights; denials raise access faults.
PMP Memory Region Definition and Creation1:37
Define the address range for a PMP region and set read, write, and execute permissions with PMP address and configuration registers, aligning the index to create indexed PMP memory regions.
PMP Programming Model and Regions Priorities6:16
Configure the PMP programming model with per-region address registers and a cfg for read, write, and execute permissions, and learn addressing modes and region priorities across supervisor and machine modes.
PMP Region Configuration Registers Overview3:53
pmp cfg registers encode read, write, and execute permissions and address matching modes for pmp regions; each 32-bit register holds four 8-bit fields for regions, scaling with pmp region count.
PMP Region Configuration Registers bits Description4:20
Describe the eight-bit pmp cfd fields per region, detailing read, write, execute permissions, address matching modes, and the lock bit that prevents updates to configuration and address registers.
PMP Region Address Register3:12
PMP Different Address Matching Modes Overview3:44
PMP TOR Address Matching Mode3:19
Describe top of range PMP mode with two registers: base at i-1 and top at i to define region; region zero base is hardwired to zero and top uses x0.
PMP NA4 Address Matching Mode1:41
Explain naturally aligned four bytes mode in the PMP region configuration, showing how the PMP address register holds the base address and fixes the region size at four bytes.
PMP NAPOT Address Matching Mode4:11
Combining Multiple PMP Addressing Modes2:57
Combine multiple PMP addressing modes, using top of range to cover flash and napot addressing mode to cover the rest, with alignment rules and two-register coverage for full protection.
PMP Region Configuration Locking Mechanism4:32
Lock PMP region by setting the locking bit to protect configuration fields and address registers; enforce read, write, and execute permissions across modes; only a hard reset clears the bit.
RISC-V Physical Memory Protection (PMP)

Lecture Introduction0:39
Explore how interrupts and exceptions work in the RISC-V processor architecture, including enabling interrupts, their execution and service routine flows, and the differences between machine mode and supervisor mode.
RISCV Different Interrupts and Exceptions Types1:39
RISCV Interrupt Handling Flow4:31
Interrupt Vector Table4:43
Store the vector table base address in a register and fetch the interrupt handler. Two bits select direct or vector mode; asynchronous interrupts use vector mode with a first-entry handler.
Difference between Direct and Vectored Interrupts handling4:46
In vector mode, derive the IRQ number from the 32-bit cause register and jump to the vector table entry by multiplying by four and adding to the vector register base.
Vector Table Structure in Vectored Mode2:29
Describe how vector mode in RISC-V uses a single vector table to handle synchronous exceptions and asynchronous interrupts, with entry zero pointing to shared handlers and entries mapping to events.
RISCV Interrupts Handling in Supervisor Mode2:00
Supervisor Mode Interrupts and Exceptions Delegation Feature1:43
Delegated Interrupts and Exceptions Execution Flow in Supervisor Mode2:54
Explore interrupts and exceptions flow in supervisor mode with and without delegation. Without delegation, the processor switches to machine mode, adding latency; delegation handles in supervisor mode, enabling real-time efficiency.
Configuration to Enable Interrupt and Exception Trapping6:55
Configure interrupt trapping by enabling the global trap in the status register, setting per-interrupt enables, and using the delegation and mep and psw registers to trap to the required mode.
RISCV (m/s)cause Register Description1:51
Describe how the RISC-V processor traps interrupts and exceptions in machine mode and supervisor mode, highlighting how indexing differs and which traps come from user, supervisor, and machine modes.

Lecture Introduction0:45
Explore fault handling to catch and manage exceptions during program execution, and learn how the RISC-V processor supports different exception types and how to pinpoint the exact faulting address.
Different RISCV Fault Exceptions Types5:43
Explore RISC-V fault exceptions types, including illegal instruction, instruction access fault, load/store access faults, and misaligned address errors, and learn how bit 31 marks synchronous versus asynchronous events.
Steps to Analyze Fault Exception4:52
Analyze a RISC-V fault by inspecting machine or supervisor registers to identify fault type and fault address, then use the saved context on the stack to locate the fault.
How to Recover from Fault Exception4:02
learn to recover a risc-v cpu from fault states via system or hard reset, or by returning from the exception after adjusting the mepc to next instruction, including supervisor mode.

Identify Our Project Tooling Dependencies2:57
Identify dependencies, packages, and tools to build and debug a Risc5 project, including myg for the makefile, cpp and ARM utilities, an LXC compiler, linker, and Sega Ozone for loading.
Tools Unique Destination Directory1:23
Install all tools and packages into a single destination directory and reference it with a Makefile variable for easy setup, with a tools installations directory provided in this Udemy course.
GnuWin32 Package Installation1:40
Acquire the make command by installing the GnuWin32 package, then locate it in the bin folder to parse and execute makefiles for embedded systems development.
Cygwin64 Package Installation6:25
riscv32-unknown-elf-gcc Toolchain and Compiler Installation5:51
Install the riscv32-unknown-elf-gcc toolchain to compile sources, generate object files, and link a final image for the 32-bit riscv processor.
Segger Ozone IDE Installation3:12
Install Segger Ozone IDE, connect to the A310 G02 i5 processor and A320 002 board, load binaries into ram or flash, and debug to explore riscv registers and device memory.
SiFive HiFive1 G002 Board Introduction1:42
Overview of the HiFive1 rev B Board from Sifive, this Board will be used as RISCV reference board to run our examples on it.
Please refer to the Get started guide of that board (see attachment), as well as the attached Board picture and below link for more details:
https://www.sifive.com/boards/hifive1-rev-b
Tools Attachment0:07

Project Introduction7:38
Prepare a makefile-driven embedded project by compiling c sources into object files to build an elf, and load the binary into flash or ram according to configuration, enabling debugging.
How to Build the Project4:26
Set up the make tool in Windows, configure PATH, and build or clean a RISC-V embedded project using flash or ram configurations, linker scripts, and map and elf outputs.
Example 00: RISCV CPU boot flow in HiFive1 G002 Board10:01
Explore the RISCV cpu boot flow on the HiFive1 G002 board, from reset handler to main, including stack and data initialization, vector table setup, and enabling interrupts.
Example 01: Machine mode to User mode switch16:10
Demonstrate switching from machine mode to user mode on RISCV processor using mpp zero, emirate, and mepc; load a user mode handler and configure PMP with Newport encoding for access.
Example 02: User mode to Machine mode switch5:38
The lecture demonstrates switching from machine mode to user mode and back via an exception call, explains vector mode and environment call from user mode in a RISC-V processor.
Example 03 Part1: Conditions to Trap Interrupt on RISCV CPU9:19
Learn how a RISC-V processor handles interrupt flow by configuring global and local enables, enabling machine timer interrupts, and placing the correct handler in the vector table.
Example 03 Part2: RISCV Interrupt Handling Explained in Details15:50
Example 04 Part1: PMP Driver Explained17:15
Example 04 Part2: PMP TOR Encoding Mode9:38
Example 05: PMP NAPOT Encoding Mode9:44
Demonstrate the PMP NAPOT encoding mode by resetting PMP registers, configuring an eight kilobyte region in Newport mode, and showing a fault when the base address is misaligned.
Attachment and Documentation0:18
The attached documents includes:
G002 SiFive Reference Manual
HiFive1B evaluation Board Get Started Guide (Board used for the course practical examples)
RISCV Privileged Specification
RISCV Debug Specification
Beside the documents we will have the riscv_project which is our riscv makefile project to be compiled and loaded as binary into the G002 CPU.

You can find as well the GitHub Repository where we have placed the RISCV Labs Project and Source Code here:
https://github.com/WadixTech/wadixcourses/tree/main/riscv-processor-architecture

Requirements

Basic knowledge on embedded systems developments as well as basic knowledge of existing processors families like X86 and ARM

Description

Does RISCV keyword tell you something or you have seen it online for sometime now? Do you want to learn RISCV Processor architecture and how does it differentiate from other Processors architectures like ARM? Do you want to write your first RISCV embedded project? Well this course is the answer for all those questions and even more!

RISCV is more than a simple keyword or basic concept that you learn one time and forget about it, RISCV Processor architecture is defining a new set of Processors to replace and compete at low cost the existing ones like ARM/X86 Processors, it is here to stay not to be forgotten!

What are you going to get from this course?

This course will help you to:

Understand RISCV Processor Architecture and how does it differentiate from other Processors Architectures.
You will see some benchmarking numbers with other Processors families like ARM.
Learn RISCV supported modes : Machine/Supervisor/User modes and how to switch between them.
Learn Interrupt handling on RISCV Processors.
Learn Different types of Exceptions and how RISCV differentiate between External Interrupts and Internal Exceptions.
Learn Fault handling and how to analyze different Faults exceptions in RISCV.
Get to know RISCV Instruction Set Architecture (ISA).
Understand PMP (Physical Memory Protection) hardware block.
Learn how to create memory protected areas in terms of access permissions using PMP Hardware Block.
Learn the difference between TOR and NAPORT address matching encoding modes supported by PMP block, as well as how to encode and program properly PMP registers with the boundaries of the memory region you want to protect.
Learn how to write C/Assembly code for your RISCV Processor.
Lear how RISCV processor is booting and executing your code base.

As part of the project you will get:

A template makefile based RISCV embedded project that you can compile and load into your RISCV device.
The project will compile and run on HiFive1 Board from SiFive company that has the G002 CPU (RISCV RV32 Processor type).
Set of tools needed to compile/load/debug your RISCV project and examples.
Set of practical examples, each one will cover some concepts/terminologies covered across this course.
To know how to Load and debug your RISCV embedded project in SiFive HiFive1 Board.
To know different RISCV processor General Purpose Registers as well as CSR Specific Functionalities Registers.

This Course is not only about RISCV Processor, is as well about how to write and develop an embedded project on RISCV based platform!

Who this course is for:

Embedded systems Students who wants to learn RISCV Processor Architecture
Embedded systems developers who wants to get hands on RISCV Architecture as quick as possible
Anyone who is curious about the RISCV architecture and want o learn about it

Mastering RISC-V Processor for Embedded Systems Programming

What you'll learn

Explore related topics

Course content

RISCV Architecture Overview7 lectures • 24min

RISCV ISA (Instruction Set Architecture)9 lectures • 25min

RISCV Internal Registers7 lectures • 18min

RISCV Different Privilege Modes7 lectures • 29min

RISCV PMP (Physical Memory Protection)12 lectures • 43min

RISCV Interrupts and Exception Handling11 lectures • 34min

RISCV Fault Handling Flow4 lectures • 15min

Setup Environment8 lectures • 23min

RISCV Practical Examples11 lectures • 1hr 46min

Requirements

Description

Who this course is for: