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Randomization and IPC in SystemVerilog
Rating: 4.4 out of 5(7 ratings)
68 students

Randomization and IPC in SystemVerilog

Simple course to learn advanced verification technique of Randomization and IPC in SystemVerilog.
Created bySurendra Rathod
Last updated 4/2021
English

What you'll learn

  • Difference between directed and random testing
  • What is randomization and why verifiation engineer should know it
  • How to do ramdomization in SystemVerilog
  • How to do constrained randomization
  • Various options available during randomization
  • How control thread execution happens in Verilog
  • Event communication in SystemVerilog
  • Semaphore in SystemVerilog
  • Mailboxes in SystemVerilog
  • How to write Testbench using IPC

Course content

9 sections • 47 lectures • 12h 42m total length

  • Welcome to Course: Introduction18:09

    Welcome and Congratulations for joining this course.

    If you know the basic SystemVerilog Constructs and exploring the possibilities of learning advanced concepts of Randomization then you have chosen the right course.

    Following are the course outcomes expected after successful completion of this course:

    Outcome 1: Ability to justify the need of randomization

    Outcome 2: Ability to write code for constrained randomization using various constructs of SystemVerilog

    Outcome 3: Ability to improve your verification skills by incorporating facilities of randomization and IPC available in SystemVerilog

    Outcome 4: Ability to justify the need for various techniques of IPC and write SystemVerilog code for the same

    Outcome 5: Ability to use inter-process communication concepts like Semaphores and Mailboxes

    Outcome 6: Ability to simulate SystemVerilog code for randomization and IPC with simulation tool and interpret simulation log


    Primary reference book for this course: Chris Spear, “System Verilog for Verification: A guide to learning the testbench language features”, Springer, 2nd Edition

    Other references:

    1. Stuart Sutherland, Simon Davidmann, and Peter Flake, “System Verilog for Design: A guide to using system verilog for hardware design and modeling”, Springer, 2nd Edition.

    2. Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari and Lisa Piper, “SystemVerilog Assertions Handbook”, VhdlCohen Publishing, 3rd edition

    3. System Verilog Language Reference manual

    4. S Prakash Rashinkar, Peter Paterson and Leena Singh, “System on Chip Verification Methodologies and Techniques”, Kluwer Academic, 1st Edition.

    Let us start learning.

  • Directed Testing6:35
  • Why Random Testing8:54
  • Let's test basic knowledge
  • Conclusion0:20

    In this session you have learned what is the difference between directed and random testing.

    You can learn more in the following manner:

    1. Consider any design of your choice, for example ethernet switch, MP3 player etc and try to write specifications for the same

    2. For the above design and its specifications try an attempt to write verification plan


      If you have successfully solved quiz and above mentioned tasks then confidently you can move to next session


      Let's get started next session. Best of luck.

Requirements

  • It is expected that knowledge of fundamentals of verification and basic constructs of SystemVerilog are known
  • Familiarity with Object Oriented Programming is an added advantage
  • Verilog programming and fundamentals of FPGA programming are supposed to be already known

Description

VLSI industry requires more verification engineers and less design engineers. Roughly this ratio is around 70 to 30 percent respectively. Because todays designs are not only very complex but also challenging to verify due to technological advancements at all the levels of design. There are many techniques that are required to be known to today's verification engineers. How to design powerful and flexible test bench is always a challenge for verification engineers. SystemVerilog provides various constructs which can ease the job of verification engineer. However one should have basic knowledge about those constructs.

This course is introduced for learners who wants to learn advanced verification techniques of randomization and inter-process communication (IPC) in SystemVerilog. It is assumed that learner is aware of the basic constructs of SystemVerilog and object oriented programming. In this course, students will learn when to do randomization, how to do constraint randomization, what are various inter-process communication techniques etc. Various IPC techniques like events, semaphores and mailboxes will be introduced. Course is being taught with various examples and learner can monitor self-progress by attempting quiz in each section. Students can try to simulate all the examples discussed in the course in EDA Playground and verify the theoretical concepts. After learning this course, students will be able to apply randomization and IPC techniques while designing test bench.

Who this course is for:

  • This course is for students and engineers who wants to learn basics of randomization and IPC in short time.
  • Verification engineers who wants to refresh concepts of randomization and IPC.

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