PyUVM Series Part 4 : Python OOPS verification env projects

Design a verification environment for a combinational 4-bit multiplier by building Mul module with two 4-bit inputs and an 8-bit output, using multiplication and continuous assignment, with dump.vcd for GTKWave.

Design and verify a D flip-flop sequential circuit by building a verification environment, wiring clock, reset, D_in, and D_out, and analyzing results with GTKWave system tasks.

Build a verification environment for a D flip-flop, apply stimulus, wait two clock ticks, sample the output, and compare it with the input to confirm correct behavior.

Construct a PyUVM verification environment for a D flip-flop, wiring generator, monitor, driver, and scoreboard through queues; apply stimuli, sample D_in and D_out, and report pass or fail.

Set up a verification test bench with queues between monitor-scoreboard and generator-driver, and perform fifo read/write transactions after reset to verify data and reach a test pass.

Design a verification environment for an SPI interface, modeling a transaction with D in data and MOSI transmission under a slowed S clock, controlled by chip select.

Design and verify a spi slave that converts 12-bit serial data from a master into parallel data, using a simple fsm and done signaling.

Modify the test bench to support both master and slave SPI transactions, using random D in values, a driver, and a scoreboard for D in versus D out.

Explore the I2C write and read transactions, including start condition, 7-bit or 10-bit addressing, MSB-first data, acknowledgments, and stop conditions.

Implement an I2C master finite state machine that handles start, address, write/read operations, acknowledgments, and stop sequences with open-drain SDA control.

Explore building a Python object-oriented I2C master verification environment, detailing start, stop, read/write operations, SDA/SCL signaling, and a multi-state FSM with acknowledgments.

Create I2C verification environment by adding data members for ports and randomizing operation type, address, and D, with address fixed at 1 and D within 50, using print_in and print_out.

Build a verification environment for a dut by simulating transmitter and receiver with random data on dtx and rx, using generator, driver, and scoreboard to compare golden data.