PyUVM Series Part 4 : Python OOPS verification env projects

Design a verification environment for a combinational 4-bit multiplier by building Mul module with two 4-bit inputs and an 8-bit output, using multiplication and continuous assignment, with dump.vcd for GTKWave.

Define Transaction class with four-bit A and B and output Y, using add_rand to generate 0–15 values; generator prints A and B via print_out and uses queue in-order simulation environment.

Develop a Python based verification environment with a driver, monitor, and scoreboard to verify a multiplier by applying stimuli to a DUT and comparing results to golden data.

Instantiate a verification environment by wiring the generator, driver, monitor, and scoreboard with queues and events, run five stimuli to the dut, and validate results using GTKWave.

Design and verify a D flip-flop sequential circuit by building a verification environment, wiring clock, reset, D_in, and D_out, and analyzing results with GTKWave system tasks.

Build a verification environment for a D flip-flop, apply stimulus, wait two clock ticks, sample the output, and compare it with the input to confirm correct behavior.

Construct a PyUVM verification environment for a D flip-flop, wiring generator, monitor, driver, and scoreboard through queues; apply stimuli, sample D_in and D_out, and report pass or fail.

Implement and verify a 16-element FIFO with 8-bit data, write/read controls, clock, reset, and empty/full status flags, plus a verification interface.

Build a fifo verification environment with a transaction class, randomized write, read, and d_in, and enforce that write and read are not the same at the same time.

Set up a verification test bench with queues between monitor-scoreboard and generator-driver, and perform fifo read/write transactions after reset to verify data and reach a test pass.

Design a verification environment for an SPI interface, modeling a transaction with D in data and MOSI transmission under a slowed S clock, controlled by chip select.

The driver generates an spi-like transaction stream for the DUT, applying reset, then transmitting 12-bit data frames with new data high, and marking transaction boundaries when chip select goes high.

Monitor samples 12-bit data from the DUT, reverses the bit order, and compares it against the expected data in the scoreboard, signaling test pass or fail.

Demonstrates a test bench with queues between generator and driver, and monitor and scoreboard, plus an event between generator and scoreboard, verifying a dut spi transmission.

Design and verify a spi slave that converts 12-bit serial data from a master into parallel data, using a simple fsm and done signaling.

Modify the test bench to support both master and slave SPI transactions, using random D in values, a driver, and a scoreboard for D in versus D out.

Explore the I2C protocol by implementing start and stop conditions, addressing, and data transfer on SDA and SCL, with a bit duration divided into four parts for FPGA timing.

Explore the I2C write and read transactions, including start condition, 7-bit or 10-bit addressing, MSB-first data, acknowledgments, and stop conditions.

Implement an I2C master finite state machine that handles start, address, write/read operations, acknowledgments, and stop sequences with open-drain SDA control.

Explore building a Python object-oriented I2C master verification environment, detailing start, stop, read/write operations, SDA/SCL signaling, and a multi-state FSM with acknowledgments.

learn how an i2c slave manages a 128-location memory with 8-bit data, including start conditions, read and write operations, and master slave synchronization.

Create I2C verification environment by adding data members for ports and randomizing operation type, address, and D, with address fixed at 1 and D within 50, using print_in and print_out.

Build a verification environment with a monitor and scoreboard to model a 128-element memory via a dictionary. Initialize memory on reset, then perform write and read operations and validate outputs.

Set up a test bench with queues, events, and component instances; execute parallel reset and main tasks, drive five memory transactions, and verify outputs against expected values for IC verification.

Design and verify a UART in Verilog, implementing transmitter and receiver with asynchronous timing, 8-bit data, start and stop bits, idle high, LSB first, and a baud clock.

Design a uart top with independent transmitter and receiver clocks, handling rx data using an lsb-first right-shift register. Set up the verification environment to test the uart module.

Build a verification environment for a dut by simulating transmitter and receiver with random data on dtx and rx, using generator, driver, and scoreboard to compare golden data.

Verify a verification bench with a monitor sampling TX and RX, reversing bits, and comparing against a scoreboard across five random transactions to ensure the DUT transmits and receives correctly.