PyUVM Series Part 2 : COCOTB fundamentals

Learn how the cocotb.test decorator executes Verilog design code from a Python testbench, displays messages on the console, applies stimuli, runs the simulation with make SIM=A, and observes DUT responses.

Explore how to apply random stimuli and read responses from a design under test (DUT) in a Python testbench, and compare results with golden data using various I/O access methods.

Compare three methods to apply values to a DUT using the value property, and generate clock, reset, and data/control signals for a 4-bit adder with A and B.

Access input and output ports by obtaining axis of a handle and applying values with the value method, then wait with a timer and analyze dum.vcd in gtk wave.

Apply stimuli directly via the value property using a handle, setting dut.a and dut.b.value to 12 and 15, then simulate and verify waveform in GTKWave.

explain three ways to assign a value to a dut in cocotb: a handle with a value property, a direct value assignment, and deprecated direct assignment operator; favor first two.

Generate reset and clock stimuli in cocotb using fixed and edge-based delays, leveraging the Timer class and triggers to apply reset for a fixed duration and observe waveform in GTKWave.

Generate a clock inside the RTL and apply reset on clock edges from the Python testbench, then access internal DUT signals with the dot operator to drive stimuli.

Learn to access internal signals of the DUT by printing and sampling the clock value using its name and value method, and use clock timing to drive reset wait conditions.

Generate a reset from clock edges in cocotb by sensing RisingEdge, FallingEdge, and Edge events and keep reset high for two positive edges before returning to zero.

Use a for loop with a five-step delay to wait for five falling edges, then set reset high. Replace with rising edges, observe reset behavior, and explore clock cycle function.

Use ClockCycle to generate reset signals by waiting for five clock edges on dut.clk, choosing rising (default) or falling edges, replacing edge waits in testbenches, and inspect with GTKWave.

Generate symmetric and asymmetric clocks for rtl verification by configuring ton, toff, and duty cycle to shape a custom clock period, using coco tb clock extensions.

Learn to compute ton and toff from user-defined frequency, duty cycle, and phase shift, convert to nanoseconds, and generate a custom clock signal with a programmable period and waveform.

Use the cocotb clock extension to generate a symmetric 10 ns clock for dut.clk with a 50% duty cycle, then simulate 100 ns to observe ten cycles and GTKWave waveform.

Explore synchronous and asynchronous functions in Cocotb for verification, showing how synchronous functions run in sequence to verify the DUT responses while asynchronous ones generate clocks and stimuli in parallel.

Explore how synchronous functions execute serially while asynchronous functions run in parallel in Cocotb. See clock signals with or without phase shifts to reveal sequential versus parallel timing.

Explore cocotb's BinaryValue extension for working with binary numbers, addressing two's complement, endianness, and initialization to ease digital verification in Python.

Explore adding values to a binary value in PyUVM's COCOTB fundamentals, using integer, signed integer, and binary string formats, with format conversions demonstrated.

Explore converting binary values to unsigned, sign-magnitude, and two’s complement representations using methods like convert_to_unsigned, convert_to_sign_magnitude, and convert_to_twos_complement.

Use Python's built-in methods to convert a value to different radix formats, including binary, hexadecimal, octal, and boolean representations. The example uses 35 to demonstrate these conversions.

Explore a four-state binary type that supports x and z values, enabling bitwise operations with shift and invert for testbench work, plus length and is resolvable checks.

Demonstrates using the BinaryValue class to implement and test a priority encoder, with an 8-bit input, 3-bit output, and a testbench validating the design against a reference model.

Build a cocotb testbench for a priority encoder using a binary value class to model an 8-bit input and 3-bit output; enable dut with 30 stimuli and 10 ns delay.

Demonstrates building a priority encoder testbench using a binary value function to generate expected outputs, verify through 30 iterations, count errors, and inspect waveforms in GTKWave.

Demonstrate cocotb based testing of integer inputs in Python by generating 30 random values 0–255, applying them to the DUT, and validating outputs against a reference module and error counting.

Understand how cocotb executes parallel coroutines using fork, start, and start soon, why fork is deprecated, and how await yields control.

Understand how the fork operation immediately starts the called task and hands control back at await, enabling cocotb task sequencing.

Learn to replace fork with start_soon to run coroutines concurrently; see how the scheduler manages tasks and awaits decide which task runs next.

Explore cocotb concurrency with fork, start_soon, and start, showing how await start immediately executes a coroutine while scheduling subsequent tasks through the scheduler.

Generate parallel stimuli for reset and clock in cocotb using async tasks and the start_soon construct. Observe concurrent execution producing reset and clock waveforms verified in gtkwave against the DUT.

Learn to verify a 4-bit adder with cocotb by building a testbench that applies random 4-bit inputs A and B, samples Y, and checks Y equals A+B with GTKWave.

Demonstrate verifying a 4-bit adder with a cocotb testbench, using adder.sv and adder_tb.py, and running make test to confirm results and observe subtractor failures.

Design and verify an 8-to-1 mux with an 8-bit input bus and 3-bit select in cocotb. The test bench uses random inputs and bit reversal compensation (7-minus-select) to check d_out.

Learn to design and verify a 4-to-1 8-bit multiplexer with four 8-bit inputs and an output selected by a 2-bit select, using a bus-based approach and a random-stimulus testbench.

Explore a 4-bit ripple carry adder built from two half adders and full adders, verified in a multi-module test bench with carry in/out and 16-based carry handling.

Verify a d flip-flop with a synchronous reset and clock, using a verification environment that applies reset in parallel, drives random d_in, and checks d_out against d_in.

Presents an 8-bit RAM with 16 locations, detailing reset, clock, write, D input, Dout, and a 4-bit address. Covers read/write operations and a dictionary-based testbench used to verify memory contents.

This lecture demonstrates memory verification with Cocotb, detailing two independent coroutines for write and read and a dictionary-backed memory model for 0–15 addresses.