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Practical FPGA project design [UART]
Rating: 4.4 out of 5(45 ratings)
2,161 students

Practical FPGA project design [UART]

Design of UART[Universal Asynchronous Receiver Transmitter], on FPGA using VHDL
Created byEzeuko Emmanuel
Last updated 1/2025
English
English [Auto],

What you'll learn

  • Simulate FPGA design using logism.
  • design UART receiver on FPGA with vhdl code, and simulate on logism
  • design UART transmitter on FPGA with vhdl code, and simulate on logism
  • Learn how to simulate and design fpga circuits in logism
  • design UART transceiver on FPGA with vhdl code, and simulate on logism

Course content

4 sections • 13 lectures • 48m total length

  • download course file0:02

    download course file.zip  from lecture 1 :course introduction below

  • Course introduction3:10

    Explore practical fpga project design by learning to build and simulate real-world applications, from basic logic to usb communication and sha-256 encryption, using free simulation tools and system-on-chip cores.

  • UART requirements4:10

    Discover the fundamentals of uart, including rs-232, baud rate, parity, start/stop bits, data bits, and duplex modes, and learn how to configure simplex, half-duplex, and full-duplex communication.

  • downloadables1:55

    Access the downloadables to see the transmitter and receiver logic in action, using the provided software and a code editor to follow along with the uart design.

  • the transmitter receiver connection4:09

    Explore simplex and duplex transmitter and receiver configurations, including the transceiver, and examine how clock, set, select signals, and signal tones govern transmission in a UART design.

  • The simulation3:55

    Explore the UART transmitter and receiver simulation, controlling transmission with clock, enable signals, and board select speed settings, then observe serial data flow and error indicators.

Requirements

  • No external hardware needed. We would simulate the FPGA design in logism. Basic knowlegde of vhdl and how to use logism may be reuired.

Description

This is a practical course, that will teach you how to design your first project on FPGA [UART - universal asynchronous transmitter and receiver.]


It explains how the vdhl code was designed. and will teach you how it was simulated , and how to trace the signals for debugging using Logism.

The course is divided into three sections: the receiver, the baud generator and transmitter.

This a 12 video course. each module teaching about a particular part of the design.

a lot of visuals, arrows, pictures were used to make the tutorials easy to understand.

kindly use the logism circuit file while watching the tutorial for easy understanding.

if my english is too fast please use the subtitle files attached.

You will design a uart transmitter and receiver . You will be able to design a transceiver by the end of the course. You will get the VHDL scripts and the logism circuit. subsequent courses will teach other serial communication protocols spi, i2c , encryption algorithm includng aes, sha256, RSA, ECDSA. Basic knowledge of vdhl is required.


View upcoming projects at projectfpga.


While on the course please download the attached files, and check links for downloads. they include logism circuit files, vhdl script. etc.


No hardware is required just your pc.


It was kept brief and straight to the point.

Who this course is for:

  • Students with basic knowledge of VHDL, looking for a project to design

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