Practical FPGA project design [UART]

Design of UART[Universal Asynchronous Receiver Transmitter], on FPGA using VHDL
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Rating: 4.6 out of 5 (4 ratings)
1,518 students
English
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Simulate FPGA design using logism.
design UART receiver on FPGA with vhdl code, and simulate on logism
design UART transmitter on FPGA with vhdl code, and simulate on logism
Learn how to simulate and design fpga circuits in logism
design UART transceiver on FPGA with vhdl code, and simulate on logism

Requirements

  • No external hardware needed. We would simulate the FPGA design in logism. Basic knowlegde of vhdl and how to use logism may be reuired.

Description

This is a practical course, that will teach you how to design your first project on FPGA [UART - universal asynchronous transmitter and receiver.]


It explains how the vdhl code was designed. and will teach you how it was simulated , and how to trace the signals for debugging using Logism.

The course is divided into three sections: the receiver, the baud generator and transmitter.

This a 12 video course. each module teaching about a particular part of the design.

a lot of visuals, arrows, pictures were used to make the tutorials easy to understand.

kindly use the logism circuit file while watching the tutorial for easy understanding.

if my english is too fast please use the subtitle files attached.

You will design a uart transmitter and receiver . You will be able to design a transceiver by the end of the course. You will get the VHDL scripts and the logism circuit. subsequent courses will teach other serial communication protocols spi, i2c , encryption algorithm includng aes, sha256, RSA, ECDSA. Basic knowledge of vdhl is required.


View upcoming projects at projectfpga.


While on the course please download the attached files, and check links for downloads. they include logism circuit files, vhdl script. etc.


No hardware is required just your pc.


It was kept brief and straight to the point.

Who this course is for:

  • Students with basic knowledge of VHDL, looking for a project to design

Course content

4 sections12 lectures48m total length
  • Course introduction
    03:10
  • UART requirements
    04:10
  • downloadables
    01:55
  • the transmitter receiver connection
    04:09
  • The simulation
    03:55

Instructor

Fpga designer, electronics , embedded system, vhdl, verilog
Ezeuko Emmanuel
  • 4.6 Instructor Rating
  • 4 Reviews
  • 1,518 Students
  • 1 Course

With over 7years designing vhdl, verilog projects on fpga.


Emmanuel is an embedded systems engineer, and currently pursuing his PH.D.He has strong knowledge in FPGA (Field Programmable Gate Array) development, Digital Electronics, Circuit Board design, and VHDL design and modeling of hardware systems using Logism. His focus of study in school was embedded systems with specialization in soc system on chip, processor core, serial communication protocols and encryption.