Physical Verification - Essential Concepts

Design rule check verifies that chip layouts meet technology constraints and density requirements across many metal layers. Foundries set these rules to ensure manufacturability and reliability.

Understand how physical verification engineers verify placement, macros, and DRC rules, including spacing, enclosure, area, length, reliability, and boundary cap considerations.

Analyze the antenna effect in plasma processing, its risk of gate oxide damage and yield loss, and practical mitigation methods using jumpers, diodes, vias, or increasing gate area.

Explore how density controls manufacturing variation in physical verification, focusing on minimum, maximum, and mean density, and compare aluminium and copper Damascene processes.

Verify softcheck and electrical rule check (ERC) to reveal layout issues, resistive layer connections, and power-ground integrity, noting warnings on ASICs.

Explore programmable electrical rule check (perc) for physical verification, enabling customizable reliability analyses beyond drc through net list analysis, current density and resistance checks for esd and overstress concerns.

Define electrostatic discharge, or ESD, as a short duration, high current event that damages VLSI circuits; poor handling and low humidity increase risk, while ESD clamps protect inputs and rails.

Latch-up arises from parasitic pnpn transistors forming a short between vdd and ground due to input, output, or supply spikes, risking device destruction; mitigate with diffusion taps and spacing.

Learn how LVS with Elvis compares layout and schematic net lists through extraction and reduction, identifying mismatches, shorts, opens, and hierarchy-aware device differences.

Explore how exclusive or (xor) logic detects changes in circuit parts and how physical verification compares base and metal layers, validating placements, taping, and partition consistency to reveal mismatches.

Drive the engineering change order (eco) process to close open physical design issues, using analysis and sign-off tools, implement fixes, and revalidate until the design is ready for the foundry.

Explore common cells seen in ICs, including standard cells, boundary end caps, decoupling capacitors, and fiduciary cells, and understand how they ensure connectivity, power integrity, and robust fabrication.

Explore physical verification concepts, including cut metal to reduce end-to-end spacing, double/triple patterning, blue/black/green box workflows, DRC considerations, and targeted interface checks across partitions.