Power Electronics Design Series: Power Factor Correction

Explore the fundamentals of the single phase diode bridge rectifier, showing how AC input converts to DC and charges the bulk capacitor through D1–D4.

Learn how a dc bulk capacitor in a diode bridge smooths rectified voltage, supports transient load energy, and enables safe shutdown and resume operation, with capacitor design equations.

Analyze diode current waveforms to determine rms and average currents, showing how alternate diodes conduct during charging, double-frequency input current, and losses related to forward voltage drop and dynamic resistance.

Power factor measures how effectively input energy is utilized over the mains period for linear and non-linear loads, aiming for unity power factor by separating real and reactive power.

Explore hold-up time in power electronics design, linking output bulk capacitance to transient ac failures, measurement methods, and the trade-off between hold-up duration and capacitor size.

The lecture explains how line impedance, mainly inductive, limits current rise and causes voltage sag, and how auto transformers smooth input current to improve power factor.

Explain inrush current at start when input applies and the output bulk capacitor charges, present limiting methods such as ntc/ptc resistors, mosfet or relay bypass, and hot-swap solutions with trade-offs.

Design a diode bridge rectifier under worst-case constant-power load using system-level conditions. Evaluate conduction times and select a 400 volt, 220 microfarad bulk capacitor with expected 2.34 amps.

Explore how non-linear loads draw harmonic currents and, using Fourier series, define power factor as the product of distortion factor and displacement factor, showing harmonics' impact on energy transfer.

Use total harmonic distortion (PhD) to measure input current quality. A direct relation shows that lower PhD yields higher power factor; e.g., 30% PhD yields 0.95 power factor.

Explore why a high power factor matters in power electronics, compare circuits with and without a DC bulk capacitor, and show how power factor correction improves efficiency and network utilization.

Explain harmonic current limits under IEC 61000-3-2, classifying equipment (A–D), mandatory PFC above 75 W, and Energy Star 80 Plus operating power factor requirements.

Achieve unity power factor by using a dc bulk capacitor as an energy buffer that stores and delivers energy to the load, causing a double-frequency ripple on the dc bus.

Explore active and passive power factor correction circuits to keep input current in phase with voltage. Learn why active PFC offers higher power factor without bulky inductors.

Explore passive power factor correction with inductors and capacitors. Compare ac-side and dc-side topologies, and note the filter inductor and input capacitor effects on conduction and harmonics.

Active power factor correction uses mosfets, diodes, and dc-dc topologies to achieve unity power factor above 0.99 and stabilize the dc bulk voltage. Placed after rectification for easier control.

Explore closed-loop control techniques for dc-dc converters and PFC, including voltage mode and current mode strategies. Understand two-loop regulation with outer voltage and inner current loops.

Explore converter operating modes, including continuous conduction mode with low peak-to-peak ripple, boundary conduction mode, and discontinuous conduction mode, where the inductor current is zero for part of the cycle.

Explore the mechanisms of active power factor correction by examining dc-dc topologies, converter operating modes, and closed-loop control techniques, and compare popular low-power pfc topologies.

Boost topology increases input current conduction time with an input-side inductor, improving power factor and reducing EMI filter size; flyback suits single-stage isolation, while buck and buck-boost cause larger EMI.

BCM boost operation underpins power factor correction for low power applications, detailing the triangular inductor current, switching dynamics, and the AC-DC block with a low-pass input filter and EMI considerations.

Explore the BCM boost converter analysis roadmap, covering on/off time, switching frequency, inductor currents, MOSFET currents, sensor resistor currents, losses, and output capacitor ripple.

Explore the on and off time analysis of a BCM boost PFC. Constant on-time yields unity power factor by shaping the input current to follow the input voltage.

Explain how maintaining constant on time in BCM Boost PFC achieves unity power factor, while off time varies, making total switching period and switching frequency variable and affecting emi.

Explore the inductor current dynamics in power factor correction: triangular current within a switching cycle, sinusoidal envelope over the line cycle, and RMS calculations for I_coil.

Learn to compute MOSFET rms currents in boost PFC by relating MOSFET current to inductor current during on cycles and tracing line-cycle variations.

Explore current sensing in power factor correction, including zero current detection and protection, and compare sensor resistor placements in negative or high-side line versus mosfet path, considering cost and accuracy.

Explore diode rms and average currents for boost pfc in bcm mode, using kcl at the output, relating diode, capacitor, and load currents to assess ac losses and steady-state conditions.

Apply KCL at boost converter output to express capacitor current as diode plus load currents, with zero average; for a resistive load, it approximates as the load current times sqrt(2).

Analyze mosfet conduction losses in boost pfc operated in bcm mode using the I^2 r_on formula with the mosfet rms current and on-state resistance.

Quantify mOSFET switching losses in a BCM boost PFC converter as energy per cycle. Turn off losses dominate; turn on losses are negligible.

Analyze conduction losses in the sense resistor using the i^2 r rule, comparing placements in the positive or negative line and in the mosfet leg.

Analyze the output capacitor ripple, dominated by a low-frequency component from energy buffering and a small high-frequency switching ripple, and derive delta v peak-to-peak.

Explore boost BCM power factor correction with constant on-time operation and variable switching frequency. Review design equations for inductors, MOSFETs, diodes, and capacitors used in boost PFC.

Examine the constant on time BCM boost PFC, highlighting simple circuitry, stable current-mode control, and no input voltage sensing, alongside drawbacks like variable switching frequency and high di/dt.

Explore BCM boost PFC controllers popular for commercial use. Most operate in voltage mode, including EMC 332621607, NCP1608, UCC 28051, UCC 38050, UCC 28056, and L6564 from STM.

Design a BCM boost PFC in current mode with MC33262. Demonstrate outer voltage and inner current loops achieving unity power factor at 85–275 V input and 400 V dc link.

Explores BCM boost PFC in voltage mode, highlighting constant on-time control without current sensing, unity power factor operation, and the similar design equations to current mode control.

Explore the limitations of BCM boost PFC, including wide switching frequency variation and EMI design challenges, and learn about frequency-clamped critical conduction mode (FC CRM) control from ON Semiconductor.

Frequency clamped critical conduction mode pfc maintains unity power factor by keeping switching frequency in dc mode and toggling between bcm and dcm based on load.

Explore how power factor correction improves PSU efficiency across 10%, 20%, 50%, and 100% loads to meet 80 plus requirements, via frequency foldback and On Semiconductor PFC controllers.

Describe controlled frequency foldback (ccff) PFC and how folding switching frequency improves efficiency at light to medium loads. Compare bcm and dcm modes with alpha, beta, skip cycle.

Explore valley switching frequency foldback for PFC, where line-voltage feedforward makes the control proportional to line current, enabling valley switching during dead time in DCM.

Explore light-load and no-load efficiency strategies for power supplies. Includes switching frequency reduction, dc bulk voltage reduction, PFC considerations, and zero-voltage switching.

Explore continuous conduction mode in CM boost PFC, where the inductor current never falls to zero within a switching period, with 20–40% ripple converging toward BCM, using BCM design equations.

Contrast BCM and CM boost PFC architectures by comparing peak-to-peak inductor current ripple, switching frequency behavior, and diode reverse recovery, and their suitability for low vs medium to high power.

Explore control schemes in CCM boost PFC, including average and peak current mode control for buck converters, and compare cycle-by-cycle versus bandwidth-based overcurrent protection and stability limits above 50% duty.

Explore the CCM boost PFC roadmap, detailing inductor coil design, MOSFET currents and losses, diode losses, sensor resistor losses, and output capacitor ripple.

Analyze the inductor and input current waveforms, highlighting high frequency ripple and the input filter's attenuation, with the input current in phase with the input voltage.

Derive the inductance design equation from on-off time equations, the duty cycle, and inductor current equations to determine the minimum inductance for CM mode operation.

Compute the mosfet rms currents for power factor correction by applying the switching period current definition and simplifying to an instantaneous magnitude expression.

Evaluate MOSFET conduction losses using the on-state resistance from the datasheet over the line period, and account for 25° to 100° temperature effects, noting ~1.5x rise.

Evaluate diode bridge conduction losses in power factor correction by average diode current and forward voltage drop. Compute total rectifier losses using pattern where two diodes conduct and multiplying factors.

Learn how MOSFET switching losses in cm mode are estimated from the overlap area of voltage and current in bcm boost PFC, then scaled by switching frequency.

Assess the two current sense resistor locations in the PFC circuit and apply the I^2R formula using I and r to estimate losses, noting the sensor value is temperature independent.

explain diode currents in boost power factor correction, show the average diode current equals the load current, and relate losses to forward voltage drop and reverse recovery losses.

Compare BCM and CCM modes, where the ripple current through the bulk capacitor is the key difference, while the ripple design equation remains the same.

Understand how ripple current in the output bulk capacitor defines CCM versus BCM operation. Apply the same DC bulk current design equation for resistive loads in DCM and CM.

Learn CM Boost PFC basics with constant switching frequency, current mode control, and summarized design equations for inductors, MOSFETs, diodes, output DC bulk capacitor, and sensor resistors.

Assess cm boost pfc advantages for medium and high power, with high factor above 0.9 and fixed switching frequency, while noting diode reverse recovery and electromagnetic interference challenges.

Explore popular CCM boost controller ICs used in commercial and automotive applications, presented in a tabular reference, and preview the CCM boost PFC design example in the next video.

Design cm boost pfc with the NCP 1654 controller, using system level specs to select inductors, diodes, bulk capacitance, and mosfets to meet ripple and hold-up.

Hysteretic control uses upper and lower limits on the control variable to switch the FET and regulate energy transfer in an open-loop, high-bandwidth PFC system.

Explains a two-loop control architecture for a hysteretic PFC with voltage loop and hysteretic current loop. Describes dynamic set points, mOSFET switching, and switching frequency variation.

Discover hysteretic mode boost PFC: simple control, excellent bandwidth, fast response, inherent stability with no loop compensation, but wide switching frequency variation near zero crossing and EMI filter design challenges.

Explore analytical control law control (acl/oc) for power factor correction, using a resettable integrator in voltage loop error amplifier to produce a variable ramp without multipliers or input voltage sensing.

Explore the advantages of ACL boost PFC, including no analog multiplier and a low-cost circuit. Identify disadvantages, such as predictive control limiting high power factors and causing steady-state voltage error.

Explore popular boost controller ICs that use the OC or ACL control strategy, including NCP1601 and NCP1653 from On Semiconductor and the IR1150 from Infineon Technologies.

Learn how interleaving combines small blocks into a larger power factor correction system, transforming disadvantages into advantages with control sequences for space-constrained applications.

Explore interleaved power factor correction with two 50 W BCM boost FCS forming a 300 W PFC converter, using 180-degree phase shift to achieve ripple-free input current and CCM behavior.

Explore interleaved two-phase BCM boost PFC designs for 300 W, showing reduced input ripple, smaller input filters, higher power density, and improved thermal performance, with trade-offs in cost and synchronization.

Explore interleaved pfc benefits—reduced emi filter, smaller dc bulk capacitor, better thermal performance, and higher efficiency for space-constrained power supplies like low-profile notebook adapters, lcd panels, and led lighting.

Power stage design of interleaved PFC, using BCM or CM boost configurations with each phase rated at half the total power, and review the related design equations.

Explore interleaved PFC controllers, including UCC 28070, UCC 28064 from Texas Instruments, Fan 96721631 from en semiconductors, and R-2r 201128, completing the interleaved PFC module discussion.

Explore why removing the diode bridge in power factor correction helps reduce bridge rectifier losses, boosting efficiency and reliability, and dive into bridgeless PFC topologies that eliminate conventional diodes.

Examine the traditional bridgeless PFC topology, where an inductor connects to the AC line and two MOSFET–diode switching cells replace diodes, with floating line voltage and EMI challenges.

Discover the two-phase bridgeless PFC design: parallel boost stages for positive and negative cycles, eliminating the diode bridge, improving efficiency, with current-sense via a transformer due to current split.

Explore bridgeless PFC topologies, including dual boost semi bridgeless PFC, bridgeless boost PFC with bi directional switch, and the totem pole variant.

Bridgeless PFC operates as two parallel boost stages with no control scheme required to switch phases, guiding low to high power power-stage design using BCM Boost PFC methods.

Explore the advantages and disadvantages of bridgeless PFC compared to traditional diode bridge rectifiers, and understand how different bridgeless PFC topologies impact power factor correction.

Explore bridgeless PFC controller ICs and how BCM enables low-power operation or CM for medium and high power, i.e., two faces in parallel, with a quick overview of popular controllers.